ISE6.1 rom16X1 initialization INIT

[Keith R. Bolson]

Hello all -

I used the source rom.vhd at the bottom of:
http://www.fpga-faq.com/FAQ_Pages/0031_How_to_initialize_Block_RAM.htm
under Webpack ISE6.1 VHDL and was surprised that XST bombs on synthesis.
FATAL_ERROR:Xstortability/export/Port_Main.h:127.1.13 -
This application has discovered an exceptional condition from which it
can not recover. Process will terminate. ...

So I tried it in webpack ISE5.1; it synthesized and simulates fine.
I tried re-installing ISE6.1 and related service packs, no change.
What am I missing?

 

[Philip Freidin]

On Sat, 10 Jan 2004 02:18:58 -0600, "Keith R. Bolson" <krbolson@visi.com> wrote:

Hello all -

I used the source rom.vhd at the bottom of:
http://www.fpga-faq.com/FAQ_Pages/0031_How_to_initialize_Block_RAM.htm
under Webpack ISE6.1 VHDL and was surprised that XST bombs on synthesis.
FATAL_ERROR:Xstortability/export/Port_Main.h:127.1.13 -
This application has discovered an exceptional condition from which it
can not recover. Process will terminate. ...

So I tried it in webpack ISE5.1; it synthesized and simulates fine.
I tried re-installing ISE6.1 and related service packs, no change.
What am I missing?

If it works in 5.1 and crashes in 6.1 then it looks like a bug.

You are not "missing" anything. Report it to Xilinx with your test case.

Philip




===================
Philip Freidin
philip@fliptronics.com
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