ISE WebPack and IPs (no CoreGen)Xilinx

[Nicolas Matringe]

Hello all
I have just downloaded the WebPack and am terribly surprised: I can't
find how to instantiate standard IP cores such as memories. CoreGen
isn't part of WebPack, so how are users supposed to use memories and so on?

Nicolas

 

[Antti Lukats]

"Nicolas Matringe" <matringenicolas001@numeri-cable.fr> wrote in message
news:410FCA53.70701@numeri-cable.fr...

Hello all
I have just downloaded the WebPack and am terribly surprised: I can't
find how to instantiate standard IP cores such as memories. CoreGen
isn't part of WebPack, so how are users supposed to use memories and so
on?

by direct instantioting ??

of start the schematics editor, place the memory primitive and later look at
the vhdl/verilog core generated for the schematics

antti
http://xilinx.openchip.org