ISE timing constraint

[Yannick]

Hi,

I need help for timing constraints in Xilinx virtex 4 Fx.

I have this design with two clocks on bufgmux and two components.

First clock : 50 Mhz
Second clock : 300 Mhz

Component A, need to work at 50Mhz
Component B, need to work at 300 Mhz

___________
| |
| |
|Component|
__________| A |
| | |
| |_________|
|
|\ |
CLK_50M ---| \ |
| \_________|
| / |
CLK_300M---| / |
|/ |
| ___________
| | |
|________| |
|Component|
| B |
|_________|

When I define both clock timing constraints on ucf file, ISE apply 300
Mhz for component A and B.
But the component A doesn't work at 300 Mhz and I don't whant that the
component A work at this frequency.

How i do for put the good frequency on each component whithout use two
bufg instead one bufgmux? (specific timing constraint)

Regards,

Yannick