ISE : Synthesis process hangs

[Rajeshwary]

We are trying to implement a decoder design on a Spartan II(2s200), and when I run the Synthesize process, the message window shows that all verilog modules are being compiled, however the process seems to take forever when it is trying the compile the unisim_comp.v file which is provided by ISE. <p>Can anybody guess what the problem could be and/or the possible solution. <p>Thanks in advance

 

[Symon]

Hi Rajeshwary,
The uniSIM library is for simulation. It has verilog models of all the
primitives that, in your case, comprise a Spartan II, so that your simulator
knows what each primitive does. You don't want or need to synthesise this,
so don't include it in your compile list.
HTH, Syms.


&lt;Rajeshwary&gt; wrote in message news:ee80e57.-1@WebX.sUN8CHnE...
We are trying to implement a decoder design on a Spartan II(2s200), and when
I run the Synthesize process, the message window shows that all verilog
modules are being compiled, however the process seems to take forever when
it is trying the compile the unisim_comp.v file which is provided by ISE.
Can anybody guess what the problem could be and/or the possible solution.
Thanks in advance