ISE and detecting flowthrus

[fpga_me]

Hi All,

When doing multi-FPGA designs, what are some of the techniques that you us
to detect if you have mistakenly pin multiplexed a flowthru net? I a
specifically interested in the way which ISE can be used.

Thanks




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Posted through http://www.FPGARelated.com

 

[Mark Curry]

In article <_sKdnTJNj4LZm8XTnZ2dnUVZ_qOdnZ2d@giganews.com>,
fpga_me <linuxfreak87@n_o_s_p_a_m.gmail.com> wrote:

Hi All,

When doing multi-FPGA designs, what are some of the techniques that you use
to detect if you have mistakenly pin multiplexed a flowthru net? I am
specifically interested in the way which ISE can be used.

You're going to have to give a few more details. I can think of a few
different cases where the term "pin multiplexed" might be used, and even
then I wouldn't like the term because of it's vagueness.

Same for "flowthru net". What's that? You made a point of indicating "multi-FPGA"
implying flowthru intra-, or inter-FPGA? And I really don't have a clue as to what
sort of problems you're trying to avoid/detect with the ISE tools.

--Mark

 

[fpga_me]

Hi Mark,

I probably used the word "flowthru" a little loosely. Essentially
flowthru would be a net that does not qualify to be pin multiplexed. Addin
multiplexing logic in its path would lead to incorrect operation. Net
which are multi-cycle in nature are examples of signals that can be adde
to pin multiplexing logic when partitioning a design across multipl
FPGAs.

In article <_sKdnTJNj4LZm8XTnZ2dnUVZ_qOdnZ2d@giganews.com>,
fpga_me <linuxfreak87@n_o_s_p_a_m.gmail.com> wrote:
Hi All,

When doing multi-FPGA designs, what are some of the techniques that yo
use
to detect if you have mistakenly pin multiplexed a flowthru net? I am
specifically interested in the way which ISE can be used.

You're going to have to give a few more details. I can think of a few
different cases where the term "pin multiplexed" might be used, and even
then I wouldn't like the term because of it's vagueness.

Same for "flowthru net". What's that? You made a point of indicatin
"multi-FPGA"
implying flowthru intra-, or inter-FPGA? And I really don't have a clu
as to what
sort of problems you're trying to avoid/detect with the ISE tools.

--Mark

---------------------------------------
Posted through http://www.FPGARelated.com