ISE 6.2 : Place problem with V2PRO

G

gilles

Guest
Dear,

I have a V2PRO design using PPC405 and several peripheral including
plb_ddr. When i try to implement my top_level deign i got the following
error during PAR :

Phase 8.24
ERROR:place:17 - The current designer locked placement of the IOBs
IMM_MASK<0> and DIMM_STROBE<0> makes this design unroutable due to a
physical routing limitation. This device has a shared routing resource
connecting the ICLK and OTCLK pins on pairs of IOBs. This restriction
means that these pairs of pins must be driven by the same signal or one
of the signals will be unroutable. Before continuing with this design
please unlock or move one of these IOBS to a new location.


I can't move then i use a AVNET Dev board so schematic is fixed !!

I use ISE / EDK 6.2 with latest Service Pack on Linux.

I found a answer record on xilinx website (N° 18780) reporting this
problem for ise 6.1 fixed with 6.1 SP3, and they say that il will be
fixed in 6.2.
But, it's still here !!!

2 questions :
- Did anyone get this kind of problem with 6.2, and what the solution ?
- It is a good idea to install ISE 6.1 SP3 on my PC ?

Thanks for your suggestions

Gilles
 
gilles wrote:
Dear,

I have a V2PRO design using PPC405 and several peripheral including
plb_ddr. When i try to implement my top_level deign i got the following
error during PAR :

Phase 8.24
ERROR:place:17 - The current designer locked placement of the IOBs
IMM_MASK<0> and DIMM_STROBE<0> makes this design unroutable due to a
physical routing limitation. This device has a shared routing resource
connecting the ICLK and OTCLK pins on pairs of IOBs. This restriction
means that these pairs of pins must be driven by the same signal or one
of the signals will be unroutable. Before continuing with this design
please unlock or move one of these IOBS to a new location.


I can't move then i use a AVNET Dev board so schematic is fixed !!

I use ISE / EDK 6.2 with latest Service Pack on Linux.

I found a answer record on xilinx website (N° 18780) reporting this
problem for ise 6.1 fixed with 6.1 SP3, and they say that il will be
fixed in 6.2.
But, it's still here !!!
Click to expand...
Hello Gilles,

The problem described in Answer 18780 is indeed fixed in version 6.2i
but you still need to set the environment variable mentioned there.

It's also possible that the problem you are seeing is unrelated to
problem described in Answer 18780. The same errors can occur for other
reasons. If you are seeing the 18780 problem, the IOB sites involved
will be located next to DCMs. Check this in FPGA Editor for
confirmation. If that is not the case, consider the possibility that the
error messages are valid and that you have a design issue.

If you do have a design issue, It may be possible to correct the problem
by controlling the FF BEL usage (BEL = IFF1|IFF2|OFF1|OFF2) or by
disabling a FF pack in the IOB (IOB = FALSE). If you are in fact needing
to get more than two input or two output clocks into a single IOB pair
then you are running into a hardware limitation with the routing
resources (Answer 11747) and there is no solution.

Regards,
Bret Wade
Xilinx Product Applications

2 questions :
- Did anyone get this kind of problem with 6.2, and what the solution ?
- It is a good idea to install ISE 6.1 SP3 on my PC ?

Thanks for your suggestions

Gilles
Click to expand...
 
gilles wrote:
Dear,

I have a V2PRO design using PPC405 and several peripheral including
plb_ddr. When i try to implement my top_level deign i got the following
error during PAR :

Phase 8.24
ERROR:place:17 - The current designer locked placement of the IOBs
IMM_MASK<0> and DIMM_STROBE<0> makes this design unroutable due to a
physical routing limitation. This device has a shared routing resource
connecting the ICLK and OTCLK pins on pairs of IOBs. This restriction
means that these pairs of pins must be driven by the same signal or one
of the signals will be unroutable. Before continuing with this design
please unlock or move one of these IOBS to a new location.


I can't move then i use a AVNET Dev board so schematic is fixed !!
Click to expand...
This is in my opinion a bug on the Avnet board. It turns out that the
IOBs in the V2Pro have the clock "hardwired" in pairs, which you can
easily see in fpga_editor. The pins for DIMM_MASK<0> and DIMM_STROBE<0>
occupy one of these pairs (P22 and R22), as do most of the other mask
and strobe signals, so they must use the same output clock. However,
this really violates the required timing for these signals.

My solution to this involved recognizing that in my application, the
mask would never change during a burst. So I used the strobe clock for
both outputs, and simply made sure that the mask signals were valid a
half clock earlier, and remained valid throughout the burst.

Another thing to be aware of. Hopefully you noticed that, because Xilinx
chose to number all there std_logic_vectors as (0 to n)???? you need to
relabel the address signal assignments in your UCF file. Otherwise, the
commands to the DDR chips won't work. For example:

# These need to be reversed from the schematic labeling,
# because Xilinx made all their VHDL models (0 to n)
NET "DDR_Addr<11>" LOC = "V25";
NET "DDR_Addr<10>" LOC = "U26";
NET "DDR_Addr<9>" LOC = "T28";
NET "DDR_Addr<8>" LOC = "T25";
NET "DDR_Addr<7>" LOC = "U27";
NET "DDR_Addr<6>" LOC = "T26";
NET "DDR_Addr<5>" LOC = "R27";
NET "DDR_Addr<4>" LOC = "R25";
NET "DDR_Addr<3>" LOC = "R28";
NET "DDR_Addr<2>" LOC = "P26";
NET "DDR_Addr<1>" LOC = "V26";
NET "DDR_Addr<0>" LOC = "M30";
#NET "DDR_Addr<12>" LOC = "P27";


--
My real email is akamail.com@dclark (or something like that).
 
"gilles" <georges@irisa.fr> wrote in message
news:cfd78b$cj2$3@amma.irisa.fr...
Dear,

I have a V2PRO design using PPC405 and several peripheral including
plb_ddr. When i try to implement my top_level deign i got the following
error during PAR :

Phase 8.24
ERROR:place:17 - The current designer locked placement of the IOBs
IMM_MASK<0> and DIMM_STROBE<0> makes this design unroutable due to a
physical routing limitation. This device has a shared routing resource
connecting the ICLK and OTCLK pins on pairs of IOBs. This restriction
means that these pairs of pins must be driven by the same signal or one
of the signals will be unroutable. Before continuing with this design
please unlock or move one of these IOBS to a new location.
Click to expand...
you can constrain one single prim to be excluded from placement into IO pad,
just specify that for one of the problematic pins in your .UCF file.
That isnt so nice solution but it makes the design to finish build with no
errors.

Antti
http://xilinx.openchip.org
 
"gilles" <georges@irisa.fr> wrote in message
news:cfd78b$cj2$3@amma.irisa.fr...
Dear,

I have a V2PRO design using PPC405 and several peripheral including
plb_ddr. When i try to implement my top_level deign i got the following
error during PAR :

Phase 8.24
ERROR:place:17 - The current designer locked placement of the IOBs
IMM_MASK<0> and DIMM_STROBE<0> makes this design unroutable due to a
physical routing limitation. This device has a shared routing resource
connecting the ICLK and OTCLK pins on pairs of IOBs. This restriction
means that these pairs of pins must be driven by the same signal or one
of the signals will be unroutable. Before continuing with this design
please unlock or move one of these IOBS to a new location.
Click to expand...
constraint guide ( cgd.pdf ) page 436

UCF/NCF
The basic syntax is:
INST "instance_name" IOB={TRUE|FALSE|AUTO};

set IOB to FALSE for one of the problem IOS the last flip flop will not be
pushed to IOB and design will map

Antti
 
Bret Wade wrote:
gilles wrote:

Dear,

I have a V2PRO design using PPC405 and several peripheral including
plb_ddr. When i try to implement my top_level deign i got the
following error during PAR :

Phase 8.24
ERROR:place:17 - The current designer locked placement of the IOBs
IMM_MASK<0> and DIMM_STROBE<0> makes this design unroutable due to a
physical routing limitation. This device has a shared routing resource
connecting the ICLK and OTCLK pins on pairs of IOBs. This restriction
means that these pairs of pins must be driven by the same signal or
one of the signals will be unroutable. Before continuing with this
design please unlock or move one of these IOBS to a new location.


I can't move then i use a AVNET Dev board so schematic is fixed !!

I use ISE / EDK 6.2 with latest Service Pack on Linux.

I found a answer record on xilinx website (N° 18780) reporting this
problem for ise 6.1 fixed with 6.1 SP3, and they say that il will be
fixed in 6.2.
But, it's still here !!!


Hello Gilles,

The problem described in Answer 18780 is indeed fixed in version 6.2i
but you still need to set the environment variable mentioned there.

It's also possible that the problem you are seeing is unrelated to
problem described in Answer 18780. The same errors can occur for other
reasons. If you are seeing the 18780 problem, the IOB sites involved
will be located next to DCMs. Check this in FPGA Editor for
confirmation. If that is not the case, consider the possibility that the
error messages are valid and that you have a design issue.

If you do have a design issue, It may be possible to correct the problem
by controlling the FF BEL usage (BEL = IFF1|IFF2|OFF1|OFF2) or by
disabling a FF pack in the IOB (IOB = FALSE). If you are in fact needing
to get more than two input or two output clocks into a single IOB pair
then you are running into a hardware limitation with the routing
resources (Answer 11747) and there is no solution.

Regards,
Bret Wade
Xilinx Product Applications


2 questions :
- Did anyone get this kind of problem with 6.2, and what the solution ?
- It is a good idea to install ISE 6.1 SP3 on my PC ?

Thanks for your suggestions

Gilles
Click to expand...

Hello,

Thanks all for your help.

Given your suggestions, i found the source of my problem.
It's not the problem report in Answer 18780 (sorry Xilinx :) ), but
effectivly a design issue.
I use the ddr clock module reference design (included in EDK) to
generate my design clk signals as mentionned in the opb ddr controller
doc (i use opb ddr and not plb not a s i write in my first post).
With this module i provide clk, clk90_in and ddr_clk90_in differential
clocks to the DDR core. The problem is that STROBE signals are generate
fron clk90_in and MASK fron clk => Hardware limitation.

Regarding Duane solution, how can i use the same clock for both signals
when use opb ddr core : sould i modify the core design itself ??

Gilles
 
gilles wrote:
...
Regarding Duane solution, how can i use the same clock for both signals
when use opb ddr core : sould i modify the core design itself ??
Click to expand...
You probably have to modify the design anyway, since the EDK core is for
a single DDR chip, and the DIMM has multiple chips on it (unless you are
not interested in using all the chips). You make a copy of the core in
your project pcores directory, name it something else, and start
modifying away. That is what I did.

--
My real email is akamail.com@dclark (or something like that).
 
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