Guest
Could someone please try the following:
In ISE 13.2, open one of the 9572XL schematic example projects (jc2_sch,
jc2_sver or jc2_svhd) and run the Floorplan IO - Pre-Synthesis process.
Does the design in the floorplanner resemble the schematic *at all*?
-a
In ISE 13.2, open one of the 9572XL schematic example projects (jc2_sch,
jc2_sver or jc2_svhd) and run the Floorplan IO - Pre-Synthesis process.
Does the design in the floorplanner resemble the schematic *at all*?
-a