ISE 10.1

J

john

Guest
Hi,

I am using ISE10.1 and trying to generate the waveform test bench for
my VHDL code. Now, the test bech waveform editor has " Initial timing
and Clock Wizard". The wizard has parameters such as Clock low time
and Clock high time, Input setup time , output valid delay etc.

My question is that Does "Input setup time" mean the Data setup time
before the rising edge of the clock and does "Output Valid time" mean
the "hold time" ? Please advice!

Regards,
John
 
john wrote:
Hi,

I am using ISE10.1 and trying to generate the waveform test bench for
my VHDL code. Now, the test bech waveform editor has " Initial timing
and Clock Wizard". The wizard has parameters such as Clock low time
and Clock high time, Input setup time , output valid delay etc.

My question is that Does "Input setup time" mean the Data setup time
before the rising edge of the clock and does "Output Valid time" mean
the "hold time" ? Please advice!

Regards,
John
Click to expand...
Hi John,
it seemed clear to me. I ran the new timing waveform wizard, and it
showed a timing diagram with the parameters you describe, and also had
the text

"Inputs are assigned at "Input Setup Time" and outputs are checked at
"Output Valid Delay"

What is not clear from that?

By the way, that wizard does not generate a VHDL testbench. If you want
to generate a VHDL testbench, use the option

Select "Behavioral Simulation" in the "Sources For:" drop-down menu,
then click on your VHDL design.

Next use
Create New Source > VHDL Testbench

regards
Alan

P.S. Beware that the VHDL Testbench wizard can write out bad code.

--
Alan Fitch
Doulos
http://www.doulos.com
 
Hi,

I am getting the following error. Do you know anything about it.

ERROR:HDLCompiler:607 - "USB_Writer_tb.vhw" Line 36. Multiple
declarations of unsigned included via multiple use clauses; none are
made directly visible


The self generating test bench option is generating the VHDL TEST
BENCH code but it has the above error. The test bench generated by
the ISE10.1 is as follows

library IEEE;
use IEEE.Std_logic_1164.ALL;
use IEEE.Numeric_std.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE STD.TEXTIO.ALL;

ENTITY USB_Writer_tb IS
END USB_Writer_tb;

ARCHITECTURE testbench_arch OF USB_Writer_tb IS
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";

COMPONENT DPR_Writer
PORT (
Data_Bus : Out UNSIGNED (13 DownTo 0);
Address_bus : Out UNSIGNED (18 DownTo 0);
Read_write : Out std_logic;
Output_Enable : Out std_logic;
CE0 : Out std_logic;
CE1 : Out std_logic;
LBL : Out std_logic;
UBL : Out std_logic;
USB_Data : In UNSIGNED (7 DownTo 0);
USB_CLK : In std_logic;
ZZL : Out std_logic;
SEML : Out std_logic;
OPTL : In std_logic;
Reset : In std_logic;
Indicator_LED : Out std_logic
);
END COMPONENT;

SIGNAL Data_Bus : UNSIGNED (13 DownTo 0) := "00000000000000";
SIGNAL Address_bus : UNSIGNED (18 DownTo 0) :=
"0000000000000000000";
SIGNAL Read_write : std_logic := '0';
SIGNAL Output_Enable : std_logic := '0';
SIGNAL CE0 : std_logic := '0';
SIGNAL CE1 : std_logic := '0';
SIGNAL LBL : std_logic := '0';
SIGNAL UBL : std_logic := '0';
SIGNAL USB_Data : UNSIGNED (7 DownTo 0) := "00000000";
SIGNAL USB_CLK : std_logic := '0';
SIGNAL ZZL : std_logic := '0';
SIGNAL SEML : std_logic := '0';
SIGNAL OPTL : std_logic := '0';
SIGNAL Reset : std_logic := '0';
SIGNAL Indicator_LED : std_logic := '0';

constant PERIOD : time := 50 ns;
constant DUTY_CYCLE : real := 0.5;
constant OFFSET : time := 0 ns;

BEGIN
UUT : DPR_Writer
PORT MAP (
Data_Bus => Data_Bus,
Address_bus => Address_bus,
Read_write => Read_write,
Output_Enable => Output_Enable,
CE0 => CE0,
CE1 => CE1,
LBL => LBL,
UBL => UBL,
USB_Data => USB_Data,
USB_CLK => USB_CLK,
ZZL => ZZL,
SEML => SEML,
OPTL => OPTL,
Reset => Reset,
Indicator_LED => Indicator_LED
);

PROCESS -- clock process for USB_CLK
BEGIN
WAIT for OFFSET;
CLOCK_LOOP : LOOP
USB_CLK <= '0';
WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
USB_CLK <= '1';
WAIT FOR (PERIOD * DUTY_CYCLE);
END LOOP CLOCK_LOOP;
END PROCESS;

PROCESS
BEGIN
WAIT FOR 100050 ns;

END PROCESS;

END testbench_arch;

Best ,

John
 
john wrote:
Hi,

I am getting the following error. Do you know anything about it.

ERROR:HDLCompiler:607 - "USB_Writer_tb.vhw" Line 36. Multiple
declarations of unsigned included via multiple use clauses; none are
made directly visible


The self generating test bench option is generating the VHDL TEST
BENCH code but it has the above error. The test bench generated by
the ISE10.1 is as follows

library IEEE;
use IEEE.Std_logic_1164.ALL;
use IEEE.Numeric_std.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE STD.TEXTIO.ALL;
Click to expand...
<snip>
You only need *either* Numeric_std *or* std_logic_arith. You can't have
both at the same time, as they both design a type UNSIGNED.

It's not clear to me which one you need as there's no arithmetic in your
code. Numeric_std is the official IEEE standard, so you might prefer to
use that.

On the other hand, you should make sure you use the same package,
whatever it is, as you used in front of your DPR_Writer entity,

regards
Alan


--
Alan Fitch
Doulos
http://www.doulos.com
 
Hi,

I commented std_logic_arith and getting the following errors

ERROR:HDLCompiler:615 - "USB_Writer.ant" Line 120. Near write ; 9
visible identifiers match here
ERROR:HDLCompiler:541 - "USB_Writer.ant" Line 120. Indexed name prefix
type void is not an array type
VHDL file USB_Writer.ant ignored due to errors
ERROR:HDLCompiler:615 - "USB_Writer.ant" Line 135. Near write ; 9
visible identifiers match here
ERROR:HDLCompiler:541 - "USB_Writer.ant" Line 135. Indexed name prefix
type void is not an array type
ERROR:HDLCompiler:854 - "USB_Writer.ant" Line 31. Unit testbench_arch
ignored due to previous errors


Regards,
John
 
john wrote:
Hi,

I commented std_logic_arith and getting the following errors

ERROR:HDLCompiler:615 - "USB_Writer.ant" Line 120. Near write ; 9
visible identifiers match here
ERROR:HDLCompiler:541 - "USB_Writer.ant" Line 120. Indexed name prefix
type void is not an array type
VHDL file USB_Writer.ant ignored due to errors
ERROR:HDLCompiler:615 - "USB_Writer.ant" Line 135. Near write ; 9
visible identifiers match here
ERROR:HDLCompiler:541 - "USB_Writer.ant" Line 135. Indexed name prefix
type void is not an array type
ERROR:HDLCompiler:854 - "USB_Writer.ant" Line 31. Unit testbench_arch
ignored due to previous errors


Regards,
John
Click to expand...
I don't understand that - it seems to be pointing to line 120, and your
posted code only has 93 lines?

I would guess it's complaining about a call to write(), but I can't see
write in your posted code,

Alan

--
Alan Fitch
Doulos
http://www.doulos.com
 
Hi,

The ISE is looking for .ant file and pointing the errors in .ant file.
It happens when I try to generate the "Self checking test bench". The
code is as follows

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 10.1
-- \ \ Application : ISE
-- / / Filename : USB_TEST.ant
-- /___/ /\ Timestamp : Thu Feb 12 16:46:47 2009
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name: USB_TEST
--Device: Xilinx
--

library IEEE;
use IEEE.Std_logic_1164.ALL;
use IEEE.Numeric_std.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
library STD;
use STD.TEXTIO.ALL;
--USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY USB_TEST IS
END USB_TEST;

ARCHITECTURE testbench_arch OF USB_TEST IS
FILE RESULTS: TEXT OPEN WRITE_MODE IS "C:\VHDL_PROGRAMS
\Phil_prj_2\sdramtst\XSA\3S1000\USB_Writer_CPLD\USB_TEST.ano";

COMPONENT DPR_Writer
PORT (
Data_Bus : Out UNSIGNED (13 DownTo 0);
Address_bus : Out UNSIGNED (18 DownTo 0);
Read_write : Out std_logic;
Output_Enable : Out std_logic;
CE0 : Out std_logic;
CE1 : Out std_logic;
LBL : Out std_logic;
UBL : Out std_logic;
USB_Data : In UNSIGNED (7 DownTo 0);
USB_CLK : In std_logic;
ZZL : Out std_logic;
SEML : Out std_logic;
OPTL : In std_logic;
Reset : In std_logic;
Indicator_LED : Out std_logic
);
END COMPONENT;

SIGNAL Data_Bus : UNSIGNED (13 DownTo 0) := "00000000000000";
SIGNAL Address_bus : UNSIGNED (18 DownTo 0) :=
"0000000000000000000";
SIGNAL Read_write : std_logic := '0';
SIGNAL Output_Enable : std_logic := '0';
SIGNAL CE0 : std_logic := '0';
SIGNAL CE1 : std_logic := '0';
SIGNAL LBL : std_logic := '0';
SIGNAL UBL : std_logic := '0';
SIGNAL USB_Data : UNSIGNED (7 DownTo 0) := "00000000";
SIGNAL USB_CLK : std_logic := '0';
SIGNAL ZZL : std_logic := '0';
SIGNAL SEML : std_logic := '0';
SIGNAL OPTL : std_logic := '0';
SIGNAL Reset : std_logic := '0';
SIGNAL Indicator_LED : std_logic := '0';

SHARED VARIABLE TX_ERROR : INTEGER := 0;
SHARED VARIABLE TX_OUT : LINE;

constant PERIOD : time := 100 ns;
constant DUTY_CYCLE : real := 0.5;
constant OFFSET : time := 0 ns;

BEGIN
UUT : DPR_Writer
PORT MAP (
Data_Bus => Data_Bus,
Address_bus => Address_bus,
Read_write => Read_write,
Output_Enable => Output_Enable,
CE0 => CE0,
CE1 => CE1,
LBL => LBL,
UBL => UBL,
USB_Data => USB_Data,
USB_CLK => USB_CLK,
ZZL => ZZL,
SEML => SEML,
OPTL => OPTL,
Reset => Reset,
Indicator_LED => Indicator_LED
);

PROCESS -- clock process for USB_CLK
BEGIN
WAIT for OFFSET;
CLOCK_LOOP : LOOP
USB_CLK <= '0';
WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
USB_CLK <= '1';
WAIT FOR (PERIOD * DUTY_CYCLE);
END LOOP CLOCK_LOOP;
END PROCESS;

PROCESS -- Annotation process for USB_CLK
VARIABLE TX_TIME : INTEGER := 0;

PROCEDURE ANNOTATE_Data_Bus(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC, string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'(", Data_Bus, "));
STD.TEXTIO.write(TX_LOC, Data_Bus);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_Address_bus(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC, string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'(", Address_bus, "));
STD.TEXTIO.write(TX_LOC, Address_bus);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_Read_write(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC, string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'(", Read_write, "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Read_write);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_Output_Enable(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC, string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'(", Output_Enable,
"));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Output_Enable);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_CE0(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC, string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'(", CE0, "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, CE0);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_CE1(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC, string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'(", CE1, "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, CE1);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_LBL(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC, string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'(", LBL, "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, LBL);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_UBL(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC, string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'(", UBL, "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, UBL);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_ZZL(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC, string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'(", ZZL, "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, ZZL);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_SEML(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC, string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'(", SEML, "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, SEML);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_Indicator_LED(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC, string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'(", Indicator_LED,
"));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Indicator_LED);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
BEGIN
WAIT for 1 fs;
ANNOTATE_Data_Bus(0);
ANNOTATE_Address_bus(0);
ANNOTATE_Read_write(0);
ANNOTATE_Output_Enable(0);
ANNOTATE_CE0(0);
ANNOTATE_CE1(0);
ANNOTATE_LBL(0);
ANNOTATE_UBL(0);
ANNOTATE_ZZL(0);
ANNOTATE_SEML(0);
ANNOTATE_Indicator_LED(0);
WAIT for OFFSET;
TX_TIME := TX_TIME + 0;
ANNO_LOOP : LOOP
--Rising Edge
WAIT for 65 ns;
TX_TIME := TX_TIME + 65;
ANNOTATE_Data_Bus(TX_TIME);
ANNOTATE_Address_bus(TX_TIME);
ANNOTATE_Read_write(TX_TIME);
ANNOTATE_Output_Enable(TX_TIME);
ANNOTATE_CE0(TX_TIME);
ANNOTATE_CE1(TX_TIME);
ANNOTATE_LBL(TX_TIME);
ANNOTATE_UBL(TX_TIME);
ANNOTATE_ZZL(TX_TIME);
ANNOTATE_SEML(TX_TIME);
ANNOTATE_Indicator_LED(TX_TIME);
WAIT for 35 ns;
TX_TIME := TX_TIME + 35;
END LOOP ANNO_LOOP;
END PROCESS;

PROCESS
BEGIN
-- ------------- Current Time: 135ns
WAIT FOR 135 ns;
Reset <= '1';
-- -------------------------------------
-- ------------- Current Time: 235ns
WAIT FOR 100 ns;
Reset <= '0';
-- -------------------------------------
WAIT FOR 999865 ns;

STD.TEXTIO.write(TX_OUT, string'("Total[]"));
STD.TEXTIO.writeline(RESULTS, TX_OUT);
ASSERT (FALSE) REPORT
"Success! Simulation for annotation completed"
SEVERITY FAILURE;
END PROCESS;

END testbench_arch;

Regards,

John
 
john wrote:
Hi,

The ISE is looking for .ant file and pointing the errors in .ant file.
It happens when I try to generate the "Self checking test bench". The
code is as follows
Click to expand...
OK, you need to change two lines: line 122 and line 137 as follows:

-- STD.TEXTIO.write(TX_LOC, Data_Bus);
ieee.std_logic_textio.write(TX_LOC,
std_logic_vector(Data_Bus));

-- STD.TEXTIO.write(TX_LOC, Address_bus);
ieee.std_logic_textio.write(TX_LOC,std_logic_vector(Address_Bus));


This is because Address_bus and Data_bus are of type UNSIGNED, which
does not have a version of the write procedure - hence you need to
convert them to std_logic_vector, and use the version of write in
ieee.std_logic_textio.

I guess another plan would be to use type std_logic_vector for
Address_bus and Data_bus, but I guess that's constrained by some other
requirement,

regards
Alan

--
Alan Fitch
Doulos
http://www.doulos.com
 
HI,

I did change those lines but now the ISE is crashing whenever I try to
run "Self Checking test bench"

Thanks

John
 
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