Is transaction-based debugging useful ?

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Dear All,

Cadence has pushed the transaction-based debugging concept for
many years, but it looks like many designers do not accept this
methodology, could some people out there explain the reasons ?
 
Cadence has pushed the transaction-based debugging concept for
many years, but it looks like many designers do not accept this
methodology, could some people out there explain the reasons ?


I like transaction-based modeling for TB because the model distinguishes btween
JOBs or transactions, and low-level interface signals. I used
trasnsaction-based modeling with Verilog and VHDL, but not with Testbuilder.
You can read a white paper at my site, under models and papers.

veriflang.pdf Document: Transaction-Based Verification in HDL
Ben
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------
 
vhdlcohen@aol.com (VhdlCohen) wrote in message news:<20030817160811.06890.00001541@mb-m06.aol.com>...
Cadence has pushed the transaction-based debugging concept for
many years, but it looks like many designers do not accept this
methodology, could some people out there explain the reasons ?


I like transaction-based modeling for TB because the model distinguishes btween
JOBs or transactions, and low-level interface signals. I used
trasnsaction-based modeling with Verilog and VHDL, but not with Testbuilder.
You can read a white paper at my site, under models and papers.

veriflang.pdf Document: Transaction-Based Verification in HDL
Ben
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------
Hi,

In actual scenario, in some cases, there could be lot of transactions
not exactly initiated by testbench. There could be protocol violations
during this time when the testbench is transaction based. I suggest
protocol checker followed by a transaction based testbench.

Am I on the right track ? :)

- Prasanna
 
In actual scenario, in some cases, there could be lot of transactions
not exactly initiated by testbench. There could be protocol violations
during this time when the testbench is transaction based. I suggest
protocol checker followed by a transaction based testbench.

The TB reacts to the environment. Thus, if the Device Under Test (DUT)
has a protocol violation casues by correct design (e.g., a mode), then the TB
should react accordingly. Transaction-based means the following to me.
1. TB_Client issues a transaction (a task) to a server.
2. Server interprets the task (e.g., READ), and issues the low-level protocol
for the READ.
3. DUT replies using low level protocol.
4. Server collects the received data, using the low-level protocol, and creates
a REPLY transaction to TB_Client.
5. TB_CLient may react to the REPLY transaction according to requirements.

Now for the checkers: If you use an HDL checker, the checkers reads the
TB_Client and REPLY transactions and dtermines accuracy of results. A
scoreboard may be used by teh checker.

If you use ABV with PSL, you write assertions in your RTL code that performs
during simulation white-box verification. ABV with PSL can also be used for
formal verification without simulation.

How many client/servers do you need, That depends upon the DUT.
In my book "Component Design by Example", I used 2, one set for each interface
of the UART (XMT and RCV).

MY latest book on PSL demosntrates applications of PSL for simulation.
However, the same code with additional verification directives can be used for
fomal verification.
ABV is the new paradigm shift for verification, just like computer synthesis
from RTL was a shift from manual synthesis with schematics.

----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------
 
Hi Ben,

Thanks for the comments.

I like transaction-based modeling for TB because the model distinguishes
btween
JOBs or transactions, and low-level interface signals.
Instead of saying it's useful, you said you "like" it, that's the point !!!

Cadence makes Test Builder open to the public, and makes SimVision support
transaction viewing, but it looks like designers rarely use this capability.



"VhdlCohen" <vhdlcohen@aol.com> źśźgŠóślĽóˇsťD
:20030817160811.06890.00001541@mb-m06.aol.com...
Cadence has pushed the transaction-based debugging concept for
many years, but it looks like many designers do not accept this
methodology, could some people out there explain the reasons ?


I like transaction-based modeling for TB because the model distinguishes
btween
JOBs or transactions, and low-level interface signals. I used
trasnsaction-based modeling with Verilog and VHDL, but not with
Testbuilder.
You can read a white paper at my site, under models and papers.

veriflang.pdf Document: Transaction-Based Verification in HDL
Ben
--------------------------------------------------------------------------
--
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for ABV, 2003 isbn
0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
0-7923-8115
--------------------------------------------------------------------------
----
 
Hi Prasanna,

"Prasanna" <pra_verilog@yahoo.com>
???????:feb16bd1.0308181614.562616bc@posting.google.com...
Hi,

In actual scenario, in some cases, there could be lot of transactions
not exactly initiated by testbench.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Could you give an example ?


There could be protocol violations
during this time when the testbench is transaction based. I suggest
protocol checker followed by a transaction based testbench.

Am I on the right track ? :)

- Prasanna
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
So do you mean that "AHB bus protocol checker" or something like
that is more useful than transaction viewing ?

As I know, OpenVera Assertion has a checker library that can check
AHB protocol violation, Verisity has eVC for AHB too.
 
I like transaction-based modeling for TB because the model distinguishes
btween
JOBs or transactions, and low-level interface signals.

Instead of saying it's useful, you said you "like" it, that's the point !!!
Bad terminology on my part! Ytansaction-based modeling is very useful.
I said "like" as compared to plain-old waveform stimulus with wait states.
Cadence makes Test Builder open to the public, and makes SimVision support
transaction viewing, but it looks like designers rarely use this capability.
Ben
 
Hi,
Transactions are definitely useful. The main idea of transactions as I
uderstand it to define clear functional interface between verification
modules. For me, the most important rule beating verification
environment complexity is: "divide and conquer". Modular verification
environment has huge advantages: new functions, added to such
envioronment, increase it's complexity and so design, debug and
support time not in exponential, but in linear order. Transactions
concept greatly facilitates such division by defining clear functional
interface between verification modules.

Speaking about transaction, I don't want to connect them to any tools
like TestBuilder or HVL - they may be easily implemented in pure
Verilog. For example, we may implement "input transaction interface"
using verilog tasks and "output transaction interface" using set of
registers and an event. So, if we need to pass transaction to
verification module, we simply launch module's task passing to it
transaction structure as task arguments, and if we want to sense
transaction coming out from verification module, we implement external
"watcher" which constatly monitors module's transaction event and
reads transaction registers upon event firing. This approach is
extremely useful implementing verification environment for layered
protocols: we may have as layered BFM as layered monitor, both
communicating between layers using predefined transaction structures.

As was mentioned, Cadence Simvision has now debugging support for
transaction and Verification CockPit - transaction DB, where you may
save transactions to derive functional coverage etc. Without using
Simvision, it is still easy to view transactions adding short unique
prefix for each one of transaction register name and then group them
in waveform viewer.


Regards,
Alexander Gnusin
www.TCLforEDA.net


"Cute Panda" <panda@zoo.com> wrote in message news:<bhv9n0$dmf$1@news.seed.net.tw>...
Hi Ben,

Thanks for the comments.

I like transaction-based modeling for TB because the model distinguishes
btween
JOBs or transactions, and low-level interface signals.

Instead of saying it's useful, you said you "like" it, that's the point !!!

Cadence makes Test Builder open to the public, and makes SimVision support
transaction viewing, but it looks like designers rarely use this capability.



"VhdlCohen" <vhdlcohen@aol.com> źśźgŠóślĽóˇsťD
:20030817160811.06890.00001541@mb-m06.aol.com...
Cadence has pushed the transaction-based debugging concept for
many years, but it looks like many designers do not accept this
methodology, could some people out there explain the reasons ?


I like transaction-based modeling for TB because the model distinguishes
btween
JOBs or transactions, and low-level interface signals. I used
trasnsaction-based modeling with Verilog and VHDL, but not with
Testbuilder.
You can read a white paper at my site, under models and papers.

veriflang.pdf Document: Transaction-Based Verification in HDL
Ben
--------------------------------------------------------------------------
--
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for ABV, 2003 isbn
0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
0-7923-8115
--------------------------------------------------------------------------
----
 

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