is this enable structure ok for synthesis/high speed?

[Ken]

Hi Folks,

The process below uses two enable signals ANDed together.

some_proc: process (CLK)

begin

if (CLK'event and CLK='1') then

if (CLKEN = '1') and (XYZ = '1') then

-- signal assignment

end if;

end if;

end process;

After synthesis and place and route (targetting XC2V3000-FG676-5) of a VHDL
design that uses this structure in several processes, the critical path
involves the CLKEN signal with the main delay being a net fanout of CLKEN of
52 taking 5.4 ns.

So, the question(s)

(Q1)
Is this style ok or should avoid ANDing enables just like I would avoid
ANDing a clock?

(Q2)
I think that the delay and fanout of CLKEN would be high anyway even if it
was not being ANDed with XYZ - agree?
(the critical path includes a tilo which I assume is the AND taking place
but this tilo is only 0.382 ns)

Many thanks for your time,

Ken

 

[Ray Andraka]

ANDing is fine here, although in a high speed design the and gate may cause you
some heartburn when trying to meet timing. The place and route (PAR) tools
don't do a very good job placing second level combinatorial stuff, particularly
gates with multiple loads like you have with a clock enable. Unless you are
really pushing the clock, it should be fine.


--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Ken]

Ray,

I might use a clk of 280MHz on a -5 Virtex-II and drive the ANDed enable
logic at 140MHz - do you think 140Mhz will be ok in general (not pushing it
surely?).

Thanks for your time,

Ken



"Ray Andraka" <ray@andraka.com> wrote in message
news:402BCD59.EC6C98AA@andraka.com...

ANDing is fine here, although in a high speed design the and gate may
cause you
some heartburn when trying to meet timing. The place and route (PAR)
tools
don't do a very good job placing second level combinatorial stuff,
particularly
gates with multiple loads like you have with a clock enable. Unless you
are
really pushing the clock, it should be fine.




--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759