Is this correct?

J

John

Guest
Hi

To keep this question short I've only included brief snipet's of code which
I hope show what I'm doing.

I'm designing a device in VHDL which contains a couple of state machines.
In my state machines I usually have a couple of IF statements e.g.

*** each state is clocked on the rising edge of FAST_CLK
when STATE_0 =>
if sig_x = '1' then
go to the next state
endif;

when STATE_1 =>
if sig_x = '0' then
go to another state
endif;

Now if I use the above example the state machine seems to get stuck in a
state. The only way I can overcome this is by doing the following:

p : process(FAST_CLK)
begin
if rising_edge(FAST_CLK) then
synced <= sig_x;
endif;
end process p;


*** each state is clocked on the rising edge of FAST_CLK
when STATE_0 =>
if synced = '1' then
go to the next state
endif;

when STATE_1 =>
if synced = '0' then
go to another state
endif;



So, basically I synchronize sig_x with FAST_CLK and then everything works.

Is this the correct way of doing it, or am I missing something obvious? Is
it normal to do this with every state machine?

Thanks for any info or advice,
 
Hi John
I prefer state machines and i believe state machines keep the structure of
the code tidy.
You could try this (put sig_x in the sensitivity list of the process):

p: process(sig_x)
when STATE_0 =>
if sig_x = '1' then
go to the next state
endif;

when STATE_1 =>
if sig_x = '0' then
go to another state
endif;

end process;

In this case, everything the signal six_x changes, the process (p) activates
and the current state will be processed.
Hope that helps.


"John" <John@john.com> wrote in message
news:bta2i3$8hl$1@news5.svr.pol.co.uk...
Hi

To keep this question short I've only included brief snipet's of code
which
I hope show what I'm doing.

I'm designing a device in VHDL which contains a couple of state machines.
In my state machines I usually have a couple of IF statements e.g.

*** each state is clocked on the rising edge of FAST_CLK
when STATE_0 =
if sig_x = '1' then
go to the next state
endif;

when STATE_1 =
if sig_x = '0' then
go to another state
endif;

Now if I use the above example the state machine seems to get stuck in a
state. The only way I can overcome this is by doing the following:

p : process(FAST_CLK)
begin
if rising_edge(FAST_CLK) then
synced <= sig_x;
endif;
end process p;


*** each state is clocked on the rising edge of FAST_CLK
when STATE_0 =
if synced = '1' then
go to the next state
endif;

when STATE_1 =
if synced = '0' then
go to another state
endif;



So, basically I synchronize sig_x with FAST_CLK and then everything works.

Is this the correct way of doing it, or am I missing something obvious?
Is
it normal to do this with every state machine?

Thanks for any info or advice,
Click to expand...
 
*** each state is clocked on the rising edge of FAST_CLK
when STATE_0 =
if sig_x = '1' then
go to the next state
endif;

when STATE_1 =
if sig_x = '0' then
go to another state
endif;

Now if I use the above example the state machine seems to get stuck in a
state. The only way I can overcome this is by doing the following:
Click to expand...
Which state does the FSM get stuck in? Who drives sig_x value and how does
it change when the FSM get stuck?
Probably the timing of sig_x is not your FSM expected. (i.e. sig_x = 0 all
the time when state = STATE_0 or sig_x = 1 all the time when state =
STATE_1).

Jim Wu
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips
 
"Jim Wu" <jimwu88NOOOSPAM@yahoo.com> wrote in message
news:RJ4Kb.1334$%L6.856@nwrdny01.gnilink.net...
*** each state is clocked on the rising edge of FAST_CLK
when STATE_0 =
if sig_x = '1' then
go to the next state
endif;

when STATE_1 =
if sig_x = '0' then
go to another state
endif;

Now if I use the above example the state machine seems to get stuck in a
state. The only way I can overcome this is by doing the following:

Which state does the FSM get stuck in? Who drives sig_x value and how does
it change when the FSM get stuck?
Probably the timing of sig_x is not your FSM expected. (i.e. sig_x = 0 all
the time when state = STATE_0 or sig_x = 1 all the time when state =
STATE_1).

Jim Wu
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips
Click to expand...
Thanks for you replies.

Due to timing it's important the state machine only changes state with
FAST_CLK e.g.

p : process(RST, FAST_CL:K)
if RST = '0' then
state <= STATE_0;
elsif rising_edge(FAST_CLK) then
case state is
when STATE_0 =>
etc
etc

The state machine usually get's stuck in first state, but not always. sig_x
is a clock generated from another process. The clock is definatly running
as I've seen it on an oscilliscope. FAST_CLK is an input to the FPGA, from
a timer.

Does that make the problem any clearer?

Thanks again,
 
Hi,

Read about metastability and synchronizers.

http://www.altera.com/literature/an/an042.pdf

Dan.
 
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