Is this code works like this...

D

dipesh.trivedi

Guest
hi friends,

i have the code which is like this,

always @(negedge WEN)

@(posedge clk); @(posedge clk); @(posedge clk); @(posedge
clk);
a <= 1'b1;
@(posedge clk); @(posedge clk); @(posedge clk); @(posedge
clk);
b <= 1'b1;

@(negedge WEN)

@(posedge clk); @(posedge clk); @(posedge clk); @(posedge
clk);
c <= 1'b1;
@(posedge clk); @(posedge clk); @(posedge clk); @(posedge
clk);
d <= 1'b1;

what i understood is a and b assigns when first negedge occurs on WEN.
and c and d assigns on the second negedge on WEN. is this because of
the always statement???

if i write it as follows then,

always @(negedge WEN)

@(posedge clk); @(posedge clk); @(posedge clk); @(posedge
clk);
a <= 1'b1;
@(posedge clk); @(posedge clk); @(posedge clk); @(posedge
clk);
b <= 1'b1;

always @(negedge WEN)

@(posedge clk); @(posedge clk); @(posedge clk); @(posedge
clk);
c <= 1'b1;
@(posedge clk); @(posedge clk); @(posedge clk); @(posedge
clk);
d <= 1'b1

will it assigned at the first negedge on WEN???
 
Nooooo Way.......
You need to use a counter if need to identify the number of clock
edges.

dipesh.trivedi wrote:
hi friends,

i have the code which is like this,

always @(negedge WEN)

@(posedge clk); @(posedge clk); @(posedge clk); @(posedge
clk);
a <= 1'b1;
@(posedge clk); @(posedge clk); @(posedge clk); @(posedge
clk);
b <= 1'b1;

@(negedge WEN)

@(posedge clk); @(posedge clk); @(posedge clk); @(posedge
clk);
c <= 1'b1;
@(posedge clk); @(posedge clk); @(posedge clk); @(posedge
clk);
d <= 1'b1;

what i understood is a and b assigns when first negedge occurs on WEN.
and c and d assigns on the second negedge on WEN. is this because of
the always statement???

if i write it as follows then,

always @(negedge WEN)

@(posedge clk); @(posedge clk); @(posedge clk); @(posedge
clk);
a <= 1'b1;
@(posedge clk); @(posedge clk); @(posedge clk); @(posedge
clk);
b <= 1'b1;

always @(negedge WEN)

@(posedge clk); @(posedge clk); @(posedge clk); @(posedge
clk);
c <= 1'b1;
@(posedge clk); @(posedge clk); @(posedge clk); @(posedge
clk);
d <= 1'b1

will it assigned at the first negedge on WEN???
Click to expand...
 
On 21 Jun 2006 01:42:37 -0700, "dipesh.trivedi"
<dipesh.trivedi@gmail.com> wrote:

hi Dipesh

'always' is like VHDL 'process' - it executes a block of procedural
code, and then loops around and starts the code executing
all over again, and so on. However, in Verilog an 'always'
controls EXACTLY ONE PROCEDURAL STATEMENT, so if you
want more than one line of code you must enclose it in
begin...end.

'initial' similarly controls just one procedural statement; it
causes that statement to execute exactly once, starting
at time 0 - like a VHDL process that has "wait" at the end.

So, VERY ROUGHLY, these are equivalent..

always
begin
...
...
end

process
begin
...
...
end process;

The fun starts when you give the process a sensitivity list.
In Verilog there's really no such thing as a sensitivity list.
Instead, you put an event control on the body of the
always block:

always @(...) begin
...
...
end

and this event control takes effect at the BEGINNING
of the body of the always (contrast VHDL, where a process
waits on its sensitivity list AFTER it's executed).

I think, therefore, that your understanding is correct;
the first example will drive signal a four clocks
after the first (negedge WEN), and then drive c
four clocks after the second (negedge WEN).
The second example has two always blocks running
in parallel, so that a/b and c/d are driven at the same
time.

However, your examples won't compile - you missed
the begin...end that's needed around each block of code
that's controlled by 'always'.

Note also that you can get multi-clock delays rather
nicely by using Verilog's repeat loop:

repeat (4) @posedge(clock);

One final point: I don't much like the use of "always"
for this kind of non-synthesisable waveform-generating
code. Most people, when they see "always", expect
a piece of code that executes in zero time with a
single event control (sensitivity list). So I would
prefer to rewrite your first example like this, so
it's clear to everyone that it's testbench code:

initial
forever begin// loops indefinitely, like "while (1)"
@(negedge WEN)
repeat (4) @(posedge clk);
a <= 1'b1;
repeat (4) @(posedge clk);
b <= 1'b1;
@(negedge WEN)
repeat (4) @(posedge clk);
c <= 1'b1;
repeat (4) @(posedge clk);
d <= 1'b1;
end
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
hi jonathan,

Thank you very much for replying and explaining. wel you are right.
this is a testbench code. right now i am doing verification of
different modules of micro-controller. and there are some testbenches
written in advance before me. so i was trying to understand those
testbench.

wel thank you once again.


Jonathan Bromley wrote:
On 21 Jun 2006 01:42:37 -0700, "dipesh.trivedi"
dipesh.trivedi@gmail.com> wrote:

hi Dipesh

'always' is like VHDL 'process' - it executes a block of procedural
code, and then loops around and starts the code executing
all over again, and so on. However, in Verilog an 'always'
controls EXACTLY ONE PROCEDURAL STATEMENT, so if you
want more than one line of code you must enclose it in
begin...end.

'initial' similarly controls just one procedural statement; it
causes that statement to execute exactly once, starting
at time 0 - like a VHDL process that has "wait" at the end.

So, VERY ROUGHLY, these are equivalent..

always
begin
...
...
end

process
begin
...
...
end process;

The fun starts when you give the process a sensitivity list.
In Verilog there's really no such thing as a sensitivity list.
Instead, you put an event control on the body of the
always block:

always @(...) begin
...
...
end

and this event control takes effect at the BEGINNING
of the body of the always (contrast VHDL, where a process
waits on its sensitivity list AFTER it's executed).

I think, therefore, that your understanding is correct;
the first example will drive signal a four clocks
after the first (negedge WEN), and then drive c
four clocks after the second (negedge WEN).
The second example has two always blocks running
in parallel, so that a/b and c/d are driven at the same
time.

However, your examples won't compile - you missed
the begin...end that's needed around each block of code
that's controlled by 'always'.

Note also that you can get multi-clock delays rather
nicely by using Verilog's repeat loop:

repeat (4) @posedge(clock);

One final point: I don't much like the use of "always"
for this kind of non-synthesisable waveform-generating
code. Most people, when they see "always", expect
a piece of code that executes in zero time with a
single event control (sensitivity list). So I would
prefer to rewrite your first example like this, so
it's clear to everyone that it's testbench code:

initial
forever begin// loops indefinitely, like "while (1)"
@(negedge WEN)
repeat (4) @(posedge clk);
a <= 1'b1;
repeat (4) @(posedge clk);
b <= 1'b1;
@(negedge WEN)
repeat (4) @(posedge clk);
c <= 1'b1;
repeat (4) @(posedge clk);
d <= 1'b1;
end
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Click to expand...
 
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