Is this CAM useful to implement?

[ALuPin]

Hi,

is the following CAM-implementation
synthezisable? How does a synthesis tool handle the for-loop
in real hardware?

http://www.geocities.com/deepakgeorge2000/cam.htm

 

[Wallclimber]

is the following CAM-implementation
synthezisable? How does a synthesis tool handle the for-loop
in real hardware?

http://www.geocities.com/deepakgeorge2000/cam.htm

I didn't try it, but it looks synthesizable to me.

For loops are usually synthesizable. Most popular tools can do it.
There may be some limitations though: eg. in Synopsys DC, the bounds
of the loop should be constant.

E.g. this is allowed:

for i in 0 to 255 loop
...
end loop;

this is not allowed:

for i in 0 to my_signal loop
...
end loop;

A way around this, that *is* synthesizable is this:

for i in 0 to 255 loop
if i<my_signal then
...
end if;
end loop;

The logic implementation is quite straightforward: just unroll the
loop into individual cases. As a result, you should be careful, since
lots and lots of logic may be the result.

In the case of the CAM, you will get one comparator for each of the
256 registers.

Tom Verbeure

 

[Mike Treseler]

ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0406220115.e0e4bb1@posting.google.com>...

is the following CAM-implementation synthezisable?

Maybe,
if you fix all of the spelling, syntax, and type errors.
Note that this design intends to use 512 8-bit registers.
A block-ram based CAM design might be more efficient.

How does a synthesis tool handle the for-loop
in real hardware?

One bit at a time.

-- Mike Treseler

 

[ALuPin]

I mean are the 256 steps of the clock performed within
one clock cycle?

How does a synthesis tool handle the for-loop
in real hardware?

One bit at a time.

-- Mike Treseler

 

[Just an Illusion]

Hi ALuPin,

For me, it seems synthezisable (but you have following errors:
clk'evevt -> Syntax error)

I think that design declare too lot of registers:
* 256x8 ff for tag
* 256x8 ff for data
* 8 ff for count
* 1 ff for full
* 1 ff for hit
* 8 ff for data_out

=> 4114 ff minimum

More it missing the value of data_out when reset

I think that you can split the code differently, and generate full, hit,
data_out through combinatory formula

Rgrds,
JaI


ALuPin wrote:

Hi,

is the following CAM-implementation
synthezisable? How does a synthesis tool handle the for-loop
in real hardware?

http://www.geocities.com/deepakgeorge2000/cam.htm

 

[Mike Treseler]

ALuPin wrote:

I mean are the 256 steps of the clock performed within
one clock cycle?

Yes. The synthesis netlist will sim the
same as the code.

-- Mike Treseler