R
ram
Guest
Objective : To build a neural network - lets say a trained ANN in a
FPGA
Available Resources : Xilinx Virtex-II Pro
Hi all
I have been trying to build a ANN for quite sometime. I need your
comments and criticism on the methods i followed and will be following
1. I tried to build a single neuron first ( 4 bit input ) , and i used
MAC core and LUT for implementing activation function( a managable
1024 values in LUT )
Then i continued with building 8 bit neuron, but got stuck at
implementing the LUT ( 2^20 values becoz the output of MAC is 20 bit
number )
2. Lately I came across Xilinx System Generator - A highlevel
modelling tool targetted for DSP application integrated with MATLAB
Simulink.
Its kind of cool so far, I dont have to worry abt entering 2^20 values
into LUT, just initialize ROM with the acitivation functino expression
and implementing MAC is with a multipier and adder blocks.
In fact i made it to the extend of completing the input layer of ANN
with 5 neurons.( keep in mind, its a trained network so i knew the
weights )
3. hmm, hmm System generator is cool , but I have a more cool device
Virtex-II pro with powerpc processor, now i have the choice of
implementing few things in hardware and others in software. But not
sure how hard it would be integrate components with PPC bus.
4. Are there any xilinx cores for a neuron????????!!!
waiting on your comments
Thanks
Ram
FPGA
Available Resources : Xilinx Virtex-II Pro
Hi all
I have been trying to build a ANN for quite sometime. I need your
comments and criticism on the methods i followed and will be following
1. I tried to build a single neuron first ( 4 bit input ) , and i used
MAC core and LUT for implementing activation function( a managable
1024 values in LUT )
Then i continued with building 8 bit neuron, but got stuck at
implementing the LUT ( 2^20 values becoz the output of MAC is 20 bit
number )
2. Lately I came across Xilinx System Generator - A highlevel
modelling tool targetted for DSP application integrated with MATLAB
Simulink.
Its kind of cool so far, I dont have to worry abt entering 2^20 values
into LUT, just initialize ROM with the acitivation functino expression
and implementing MAC is with a multipier and adder blocks.
In fact i made it to the extend of completing the input layer of ANN
with 5 neurons.( keep in mind, its a trained network so i knew the
weights )
3. hmm, hmm System generator is cool , but I have a more cool device
Virtex-II pro with powerpc processor, now i have the choice of
implementing few things in hardware and others in software. But not
sure how hard it would be integrate components with PPC bus.
4. Are there any xilinx cores for a neuron????????!!!
waiting on your comments
Thanks
Ram