Is there something in verilog similar to #if in C++?

[Peng Yu]

Hi,
When I want to commend some code in C++, I could either use /**/ or
#if 0 #endif pair. However, I don't find a compiler directive in
verilog, which is similar to #if in C++.
However, in some situation, #if 0 #endif pair is convenient. The
following is an example for C++.

#if 0
printf("Hello\n");
/*printf("Hello\n");*/
printf("Hello\n");
/*printf("Hello\n");*/
printf("Hello\n");
#endif

In this case some code commented with /**/ is with the scope of the
code that you're going to comment later. Instead of deleting all the
/**/ in the body and putting a pair of /**/ at both the begining and
the end, #if 0 #endif pair is the best solution.
I wonder whether verilog support this syntax. Thanks!

Peng

 

[Stephen Williams]

Peng Yu wrote:

#if 0
printf("Hello\n");
/*printf("Hello\n");*/
printf("Hello\n");
/*printf("Hello\n");*/
printf("Hello\n");
#endif

Verilog has `ifdef/`endif that you can use like so:

`ifdef XXXX
comment me out.
`endif

I often use XXXX as a generic undefined symbol for this
very purpose.

--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

 

[Peng Yu]

Stephen Williams <spamtrap@icarus.com> wrote in message news:<bgvb3g$r3i$1@sun-news.laserlink.net>...

Verilog has `ifdef/`endif that you can use like so:

`ifdef XXXX
comment me out.
`endif

I often use XXXX as a generic undefined symbol for this
very purpose.

But this may result in some problem, if you define XXX somewhere eventually.

 

[Stephen Williams]

Peng Yu wrote:

Stephen Williams <spamtrap@icarus.com> wrote in message news:<bgvb3g$r3i$1@sun-news.laserlink.net>...

Verilog has `ifdef/`endif that you can use like so:

`ifdef XXXX
comment me out.
`endif

I often use XXXX as a generic undefined symbol for this
very purpose.


But this may result in some problem, if you define XXX somewhere eventually.

OK, if we are being picky, maybe this will be slightly better:

`ifdef DoNotDefineThisSymbolUnderPenaltyOfDeathStompStompStomp
commented out stuff
`endif

There is no general preprocessor "if" in Verilog. The effect you
desire can be achieved trivially with the smallest bit of discipline.

--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

 

[Peng Yu]

Chris F Clark <cfc@shell01.TheWorld.com> wrote in message news:<sddptjf96jw.fsf@shell01.TheWorld.com>...

Finally, since Verilog has // (C++ style) comments, you can use them
to effectively comment out code leaving a nice visual marker on each
line--some editors (e.g. emacs) have functions that apply and remove
C++ comments to (and from) a region.
I always use vi to edit text files. I want to know whether vi has

those functions? If vi doesn't, I'll consider switch to emacs. Thanks!