Is there anyway to pass "arguments" to a Verilog testbench?

[mrfirmware]

I've inhereted some testbench code that reads some input data from a
hardcoded input dir and writes some results to a hardcoded output dir.
I'd like to specify both the input and output dirs at simulation time.
Is this possible? If so, how?

Thanks,
- Mark

 

[mrfirmware]

On Jul 24, 4:53 pm, mrfirmware <mrfirmw...@gmail.com> wrote:

I've inhereted some testbench code that reads some input data from a
hardcoded input dir and writes some results to a hardcoded output dir.
I'd like to specify both the input and output dirs at simulation time.
Is this possible? If so, how?

Nevermind, I finally found it. $value$plusargs did the trick.

Sorry for wasting bandwidth,
- Mark