Is there any way to catch incorrect vector assignment?

I've recently spent more than four hours just trying to catch two
trivial incorrect vector assignments (incorrectly declaring vector as
scalar & 3-bit vector as 4-bit vector) in Verilog design modules.
I'm fairly new to Verilog, and I'm not that comfortable with using
ModelSim or analyzing Verilog codes yet.
So, just in case I make similar mistake some time later, I was
wondering if there is any function in ModelSim that catches those kind
of mistakes, like printing out a warning on the screen when there is a
mismatch in the size of a vector or something.

 

[glen herrmannsfeldt]

xicloid@gmail.com wrote:

I've recently spent more than four hours just trying to catch two
trivial incorrect vector assignments (incorrectly declaring vector as
scalar & 3-bit vector as 4-bit vector) in Verilog design modules.
I'm fairly new to Verilog, and I'm not that comfortable with using
ModelSim or analyzing Verilog codes yet.

Then there are those that give a warning when verilog says
that they should not(*). If there are enough warnings that
should not be there, you will miss those that you should see.

(*) I believe it is adding two N bit numbers generates an
N bit sum, but some would generate N+1 bits and a warning.

-- glen

 

[GilGr]

On Apr 25, 9:02 am, xicl...@gmail.com wrote:

I've recently spent more than four hours just trying to catch two
trivial incorrect vector assignments (incorrectly declaring vector as
scalar & 3-bit vector as 4-bit vector) in Verilog design modules.
I'm fairly new to Verilog, and I'm not that comfortable with using
ModelSim or analyzing Verilog codes yet.
So, just in case I make similar mistake some time later, I was
wondering if there is any function in ModelSim that catches those kind
of mistakes, like printing out a warning on the screen when there is a
mismatch in the size of a vector or something.

as said before, different compilers behave differently. What compiler
are you using? I'm using VCS, and warnings like the ones you are
looking for are not enbaled bt default, and you should use the linter,
by adding +lint+PCWM to check for port width mismatches. You can read
more in the compiler manual

Gil.