Is there any software I can use to transform state machines in VHDL into drawings?...

T

Tianxiang Weng

Guest
Hi,
I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings.

Is there any software I can use to transform state machines in VHDL into drawings?

Thank you.

Weng
 
On Wednesday, September 8, 2021 at 4:24:49 PM UTC-4, Tianxiang Weng wrote:
Hi,
I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings.

Is there any software I can use to transform state machines in VHDL into drawings?

Thank you.

Weng
Click to expand...

Questasim has a FSM debugger option that generates a graphical view of your state machine, but it\'s not always a great view for documentation purposes.
 
On Wednesday, September 8, 2021 at 4:24:49 PM UTC-4, Tianxiang Weng wrote:
Hi,
I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings.

Is there any software I can use to transform state machines in VHDL into drawings?

Thank you.

Weng
Click to expand...

Questasim has a FSM debugger option that generates a graphical view of your state machine, but it\'s not always a great view for documentation purposes.
 
On Wednesday, September 8, 2021 at 4:24:49 PM UTC-4, Tianxiang Weng wrote:
Hi,
I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings.

Is there any software I can use to transform state machines in VHDL into drawings?

Thank you.

Weng
Click to expand...

Questasim has a FSM debugger option that generates a graphical view of your state machine, but it\'s not always a great view for documentation purposes.
 
On Wednesday, September 8, 2021 at 4:24:49 PM UTC-4, Tianxiang Weng wrote:
Hi,
I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings.

Is there any software I can use to transform state machines in VHDL into drawings?

Thank you.

Weng
Click to expand...

Questasim has a FSM debugger option that generates a graphical view of your state machine, but it\'s not always a great view for documentation purposes.
 
On Thursday, September 9, 2021 at 8:01:46 AM UTC-7, kkoorndyk wrote:
On Wednesday, September 8, 2021 at 4:24:49 PM UTC-4, Tianxiang Weng wrote:
Hi,
I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings.

Is there any software I can use to transform state machines in VHDL into drawings?

Thank you.

Weng
Questasim has a FSM debugger option that generates a graphical view of your state machine, but it\'s not always a great view for documentation purposes.
Click to expand...

What I have been developing is a set of new hardware circuits that have been never used. I want to apply for patents with full state machines design disclosed. For correctness, the state machines block diagrams should be consistent with the source code in VHDL. So I am seeking such tools. Now I have to draw block diagrams manually, it may introduce inconsistence.

Weng
 
On Thursday, September 9, 2021 at 8:01:46 AM UTC-7, kkoorndyk wrote:
On Wednesday, September 8, 2021 at 4:24:49 PM UTC-4, Tianxiang Weng wrote:
Hi,
I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings.

Is there any software I can use to transform state machines in VHDL into drawings?

Thank you.

Weng
Questasim has a FSM debugger option that generates a graphical view of your state machine, but it\'s not always a great view for documentation purposes.
Click to expand...

What I have been developing is a set of new hardware circuits that have been never used. I want to apply for patents with full state machines design disclosed. For correctness, the state machines block diagrams should be consistent with the source code in VHDL. So I am seeking such tools. Now I have to draw block diagrams manually, it may introduce inconsistence.

Weng
 
On Thursday, September 9, 2021 at 8:01:46 AM UTC-7, kkoorndyk wrote:
On Wednesday, September 8, 2021 at 4:24:49 PM UTC-4, Tianxiang Weng wrote:
Hi,
I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings.

Is there any software I can use to transform state machines in VHDL into drawings?

Thank you.

Weng
Questasim has a FSM debugger option that generates a graphical view of your state machine, but it\'s not always a great view for documentation purposes.
Click to expand...

What I have been developing is a set of new hardware circuits that have been never used. I want to apply for patents with full state machines design disclosed. For correctness, the state machines block diagrams should be consistent with the source code in VHDL. So I am seeking such tools. Now I have to draw block diagrams manually, it may introduce inconsistence.

Weng
 
On Thursday, September 9, 2021 at 8:01:46 AM UTC-7, kkoorndyk wrote:
On Wednesday, September 8, 2021 at 4:24:49 PM UTC-4, Tianxiang Weng wrote:
Hi,
I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings.

Is there any software I can use to transform state machines in VHDL into drawings?

Thank you.

Weng
Questasim has a FSM debugger option that generates a graphical view of your state machine, but it\'s not always a great view for documentation purposes.
Click to expand...

What I have been developing is a set of new hardware circuits that have been never used. I want to apply for patents with full state machines design disclosed. For correctness, the state machines block diagrams should be consistent with the source code in VHDL. So I am seeking such tools. Now I have to draw block diagrams manually, it may introduce inconsistence.

Weng
 
Tianxiang Weng <wtxwtx@gmail.com> schrieb:
On Thursday, September 9, 2021 at 8:01:46 AM UTC-7, kkoorndyk wrote:
On Wednesday, September 8, 2021 at 4:24:49 PM UTC-4, Tianxiang Weng wrote:
Hi,
I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings.

Is there any software I can use to transform state machines in VHDL into drawings?

Thank you.

Weng
Questasim has a FSM debugger option that generates a graphical view of your state machine, but it\'s not always a great view for documentation purposes.

What I have been developing is a set of new hardware circuits that have been never used. I want to apply for patents with full state machines design disclosed. For correctness, the state machines block diagrams should be consistent with the source code in VHDL. So I am seeking such tools. Now I have to draw block diagrams manually, it may introduce inconsistence.
Click to expand...

You could use https://github.com/hneemann/Digital to draw your state
machines, then export to VHDL.
 
Tianxiang Weng <wtxwtx@gmail.com> schrieb:
On Thursday, September 9, 2021 at 8:01:46 AM UTC-7, kkoorndyk wrote:
On Wednesday, September 8, 2021 at 4:24:49 PM UTC-4, Tianxiang Weng wrote:
Hi,
I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings.

Is there any software I can use to transform state machines in VHDL into drawings?

Thank you.

Weng
Questasim has a FSM debugger option that generates a graphical view of your state machine, but it\'s not always a great view for documentation purposes.

What I have been developing is a set of new hardware circuits that have been never used. I want to apply for patents with full state machines design disclosed. For correctness, the state machines block diagrams should be consistent with the source code in VHDL. So I am seeking such tools. Now I have to draw block diagrams manually, it may introduce inconsistence.
Click to expand...

You could use https://github.com/hneemann/Digital to draw your state
machines, then export to VHDL.
 
Tianxiang Weng <wtxwtx@gmail.com> schrieb:
On Thursday, September 9, 2021 at 8:01:46 AM UTC-7, kkoorndyk wrote:
On Wednesday, September 8, 2021 at 4:24:49 PM UTC-4, Tianxiang Weng wrote:
Hi,
I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings.

Is there any software I can use to transform state machines in VHDL into drawings?

Thank you.

Weng
Questasim has a FSM debugger option that generates a graphical view of your state machine, but it\'s not always a great view for documentation purposes.

What I have been developing is a set of new hardware circuits that have been never used. I want to apply for patents with full state machines design disclosed. For correctness, the state machines block diagrams should be consistent with the source code in VHDL. So I am seeking such tools. Now I have to draw block diagrams manually, it may introduce inconsistence.
Click to expand...

You could use https://github.com/hneemann/Digital to draw your state
machines, then export to VHDL.
 
On Friday, September 10, 2021 at 3:24:05 AM UTC-7, Thomas Koenig wrote:
Tianxiang Weng <wtx...@gmail.com> schrieb:
On Thursday, September 9, 2021 at 8:01:46 AM UTC-7, kkoorndyk wrote:
On Wednesday, September 8, 2021 at 4:24:49 PM UTC-4, Tianxiang Weng wrote:
Hi,
I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings.

Is there any software I can use to transform state machines in VHDL into drawings?

Thank you.

Weng
Questasim has a FSM debugger option that generates a graphical view of your state machine, but it\'s not always a great view for documentation purposes.

What I have been developing is a set of new hardware circuits that have been never used. I want to apply for patents with full state machines design disclosed. For correctness, the state machines block diagrams should be consistent with the source code in VHDL. So I am seeking such tools. Now I have to draw block diagrams manually, it may introduce inconsistency.
You could use https://github.com/hneemann/Digital to draw your state
machines, then export to VHDL.
Click to expand...

Thomas Koenig,
I reviewed the website https://github.com/hneemann/Digital; it is a wonderful product, but I prefer my coding practice: using VHDL and drawing mutually to complete a complex state machine. I use Intel Visio to draw state machine block diagrams.

When reviewing a state machine design, it is easier to use state machine block diagrams.

Thank you.

Weng
 
On Friday, September 10, 2021 at 3:24:05 AM UTC-7, Thomas Koenig wrote:
Tianxiang Weng <wtx...@gmail.com> schrieb:
On Thursday, September 9, 2021 at 8:01:46 AM UTC-7, kkoorndyk wrote:
On Wednesday, September 8, 2021 at 4:24:49 PM UTC-4, Tianxiang Weng wrote:
Hi,
I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings.

Is there any software I can use to transform state machines in VHDL into drawings?

Thank you.

Weng
Questasim has a FSM debugger option that generates a graphical view of your state machine, but it\'s not always a great view for documentation purposes.

What I have been developing is a set of new hardware circuits that have been never used. I want to apply for patents with full state machines design disclosed. For correctness, the state machines block diagrams should be consistent with the source code in VHDL. So I am seeking such tools. Now I have to draw block diagrams manually, it may introduce inconsistency.
You could use https://github.com/hneemann/Digital to draw your state
machines, then export to VHDL.
Click to expand...

Thomas Koenig,
I reviewed the website https://github.com/hneemann/Digital; it is a wonderful product, but I prefer my coding practice: using VHDL and drawing mutually to complete a complex state machine. I use Intel Visio to draw state machine block diagrams.

When reviewing a state machine design, it is easier to use state machine block diagrams.

Thank you.

Weng
 
On Friday, September 10, 2021 at 3:24:05 AM UTC-7, Thomas Koenig wrote:
Tianxiang Weng <wtx...@gmail.com> schrieb:
On Thursday, September 9, 2021 at 8:01:46 AM UTC-7, kkoorndyk wrote:
On Wednesday, September 8, 2021 at 4:24:49 PM UTC-4, Tianxiang Weng wrote:
Hi,
I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings.

Is there any software I can use to transform state machines in VHDL into drawings?

Thank you.

Weng
Questasim has a FSM debugger option that generates a graphical view of your state machine, but it\'s not always a great view for documentation purposes.

What I have been developing is a set of new hardware circuits that have been never used. I want to apply for patents with full state machines design disclosed. For correctness, the state machines block diagrams should be consistent with the source code in VHDL. So I am seeking such tools. Now I have to draw block diagrams manually, it may introduce inconsistency.
You could use https://github.com/hneemann/Digital to draw your state
machines, then export to VHDL.
Click to expand...

Thomas Koenig,
I reviewed the website https://github.com/hneemann/Digital; it is a wonderful product, but I prefer my coding practice: using VHDL and drawing mutually to complete a complex state machine. I use Intel Visio to draw state machine block diagrams.

When reviewing a state machine design, it is easier to use state machine block diagrams.

Thank you.

Weng
 
Tianxiang Weng <wtxwtx@gmail.com> wrote:
When reviewing a state machine design, it is easier to use state machine
block diagrams.
Click to expand...

A codebase I look after puts $display statements in the code that print
Graphviz code for each state in the state machine. The testbench exercises
the code to pass through all the states. When run, you pipe the output into
a .dot file and feed that into Graphviz, which will generate a PNG, SVG,
PDF of the state transition diagram.

It\'s a hack, but it works well enough.

Theo
 
Tianxiang Weng <wtxwtx@gmail.com> wrote:
When reviewing a state machine design, it is easier to use state machine
block diagrams.
Click to expand...

A codebase I look after puts $display statements in the code that print
Graphviz code for each state in the state machine. The testbench exercises
the code to pass through all the states. When run, you pipe the output into
a .dot file and feed that into Graphviz, which will generate a PNG, SVG,
PDF of the state transition diagram.

It\'s a hack, but it works well enough.

Theo
 
Tianxiang Weng <wtxwtx@gmail.com> wrote:
When reviewing a state machine design, it is easier to use state machine
block diagrams.
Click to expand...

A codebase I look after puts $display statements in the code that print
Graphviz code for each state in the state machine. The testbench exercises
the code to pass through all the states. When run, you pipe the output into
a .dot file and feed that into Graphviz, which will generate a PNG, SVG,
PDF of the state transition diagram.

It\'s a hack, but it works well enough.

Theo
 
I believe the Sigasi editor has something like that: https://insights.sigasi.com/manual/views/#state-machine-view

Cheers,
Guy.

On Wednesday, September 8, 2021 at 10:24:49 PM UTC+2, Tianxiang Weng wrote:
Hi,
I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings.

Is there any software I can use to transform state machines in VHDL into drawings?

Thank you.

Weng
Click to expand...
 
I believe the Sigasi editor has something like that: https://insights.sigasi.com/manual/views/#state-machine-view

Cheers,
Guy.

On Wednesday, September 8, 2021 at 10:24:49 PM UTC+2, Tianxiang Weng wrote:
Hi,
I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings.

Is there any software I can use to transform state machines in VHDL into drawings?

Thank you.

Weng
Click to expand...
 
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