IS there any open-sourse tool to convert SystemVerilog to Ve

[Nasrin Eshraghi]

Hello

I have codes wanting to have output as a Verilog code, Is there any tool which can do it?


Many thanks

 

[dsc]

What do you mean? System Verilog is completely based on Verilog + extra. What kind of output do you need? There won’t be a tool such as that. (Not a perfect example but would be like having a tool to turn C++ into C.)