Is there a way to use generics in verilog?

[Frank]

Hi,

Is it possible to use generics is verilog?

In vhdl this would like this:
ENTITY timing IS
GENERIC (width_delayOSITIVE; -- delay adjustment bus width
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
out : OUT STD_LOGIC
);
END timing;

So when the module is instantiated I would like to use a different
width_delay parameter for each instantiation

Regards,

Frank

So I want to instantiate the module multiple times but with a different
value of width_delay.

Thanks Frank

 

[Renaud Pacalet]

Frank wrote:

Hi,

Is it possible to use generics is verilog?

In vhdl this would like this:
ENTITY timing IS
GENERIC (width_delayOSITIVE; -- delay adjustment bus width
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
out : OUT STD_LOGIC
);
END timing;

So when the module is instantiated I would like to use a different
width_delay parameter for each instantiation

What you need is named "parameter":

module Timing(Clock, Reset, Out);
parameter WidthDelay = 16;
...

When instanciating your module you can specify a value for WidthDelay:
- directly:
Timing #(32) T1(.Clock(A), .Reset(B), .Out(C));
- with another parameter:
parameter Wd = 32;
Timing #(Wd) T1(.Clock(A), .Reset(B), .Out(C));

Depending on your simulator you can specify parameters values on the
command line:

vsim -GWd=64 ...

Regards,
--
Renaud Pacalet, ENST, 46 rue Barrault 75634 Paris Cedex 13
###### Tel. : 01 45 81 78 08 | Fax : 01 45 80 40 36 ######
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[Frank]

Hi Renaud,

Thanks for your quick response this is exactly where I was looking for.

Frank

"Renaud Pacalet" <MonPrenom.MonNom@PasDeSpam.MonOrganisation.France> wrote
in message news:bj9sda$1cmd$1@avanie.enst.fr...

Frank wrote:
Hi,

Is it possible to use generics is verilog?

In vhdl this would like this:
ENTITY timing IS
GENERIC (width_delayOSITIVE; -- delay adjustment bus width
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
out : OUT STD_LOGIC
);
END timing;

So when the module is instantiated I would like to use a different
width_delay parameter for each instantiation

What you need is named "parameter":

module Timing(Clock, Reset, Out);
parameter WidthDelay = 16;
...

When instanciating your module you can specify a value for WidthDelay:
- directly:
Timing #(32) T1(.Clock(A), .Reset(B), .Out(C));
- with another parameter:
parameter Wd = 32;
Timing #(Wd) T1(.Clock(A), .Reset(B), .Out(C));

Depending on your simulator you can specify parameters values on the
command line:

vsim -GWd=64 ...

Regards,
--
Renaud Pacalet, ENST, 46 rue Barrault 75634 Paris Cedex 13
###### Tel. : 01 45 81 78 08 | Fax : 01 45 80 40 36 ######
# Fight Spam! Join EuroCAUCE: http://www.euro.cauce.org/ #