W
walala
Guest
Dear all,
I want to ask a question about FILE I/O using Verilog during
simulation. My project requires a close collaboration between matlab
and Verilog simulation. I need to import data generated from matlab
into Verilog program and then execute and get results exported into
matlab for further analysis.
Is there a way to open/save file for exchanging data in Verilog?
Thanks a lot,
-Walala
I want to ask a question about FILE I/O using Verilog during
simulation. My project requires a close collaboration between matlab
and Verilog simulation. I need to import data generated from matlab
into Verilog program and then execute and get results exported into
matlab for further analysis.
Is there a way to open/save file for exchanging data in Verilog?
Thanks a lot,
-Walala