is there a way to convert an array to an output port??

K

krby_xtrm

Guest
is there a way to convert an array to an output port??


....

port
(
clk : in std_logic;
ramin : in std_logic_vector (15 downto 0); -- input vector
ram_sel : in integer range 0 to 23; -- selects w/c ram data will ramin
go
ram_data : buffer expander_array (1 to 192) -- 192 16-bit Register

);

...
when i create a symbol for this with quartus_ii it complains that port
(ram_data) cannot be a 'complex type'.

my intention is for this component to output 3072-bit (192*16)
what could be the solution? will converting this complex type to a
3072-bit vector will do? or is it possible?
 
"krby_xtrm" <kerby.martino@gmail.com> writes:

is there a way to convert an array to an output port??


...

port
(
clk : in std_logic;
ramin : in std_logic_vector (15 downto 0); -- input vector
ram_sel : in integer range 0 to 23; -- selects w/c ram data will ramin
go
ram_data : buffer expander_array (1 to 192) -- 192 16-bit Register

);

..
when i create a symbol for this with quartus_ii it complains that port
(ram_data) cannot be a 'complex type'.
Click to expand...
Have you tried making a seperate type for this, e.g.:
type ram_data_array_t is exander_array(1 to 192);
and then using ram_data_array_t as type for ram_daa in the port
definition?


Kai
--
Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>
 
yeah. ram_data is actually an output port of the design, but i need raw
bits, i.e 3072-bit output port, these ports are internal to a more
higher level design in the heirarchy so its no actual pins of the
device, but rather interconnects...
 
krby_xtrm wrote:
is there a way to convert an array to an output port??
...

port
(
clk : in std_logic;
ramin : in std_logic_vector (15 downto 0); -- input vector
ram_sel : in integer range 0 to 23; -- selects w/c ram data will ramin
go
ram_data : buffer expander_array (1 to 192) -- 192 16-bit Register

);
Click to expand...
Don't use "buffer", pretty much ever. If you need to use the signal
internally and also output it, then create an internal signal
expander_array_i
Use that internally. Then assign the output.
expander_array <= expander_array_i;
 
what is expander_array_i in that code? in expander_array <=
expander_array_i; ??
is it:
signal ram_data : expander_array; ??

so how can i put it this way say,
i have an output port 'b' and i want two of the array in ram_data w/c
is a 16-bit register (std_logic_vector )
i think this works:
....
signal b : std_logic_vector (35 downto 0)
b <= ram_data(1) & ram_data(2); -- both 16-bit
....

but how about this?
....
signal c: std_logic_vector(3071 downto 0); -- 192 16-bit registers,
pretty large
b <= ram_data(1) & ram_data(2) ... ram_data(190) & ram_data(191)...etc

it would cover all of the space/ is there a way to minimize such
typing... don't look at it that i just don't like to type... there are
reasons....

is there a way?>, above all i need is what i explained at the top....

regards,
krby_Xtrm
 
krby_xtrm wrote:
what is expander_array_i in that code? in expander_array <=
expander_array_i; ??
is it:
signal ram_data : expander_array; ??
Click to expand...
Oops, careless of me. I meant to use an internal signal for ram_data,
not expander_array.

so how can i put it this way say,
i have an output port 'b' and i want two of the array in ram_data w/c
is a 16-bit register (std_logic_vector )
i think this works:
...
signal b : std_logic_vector (35 downto 0)
b <= ram_data(1) & ram_data(2); -- both 16-bit
...

but how about this?
...
signal c: std_logic_vector(3071 downto 0); -- 192 16-bit registers,
pretty large
b <= ram_data(1) & ram_data(2) ... ram_data(190) & ram_data(191)...etc

it would cover all of the space/ is there a way to minimize such
typing... don't look at it that i just don't like to type... there are
reasons....
Click to expand...
b_v := ram_data(1);
for i in 2 to 191 loop
b_v := b_v & ram_data(i);
end loop
b <= b_v;
 
Duane Clark wrote:
b_v := ram_data(1);
for i in 2 to 191 loop
b_v := b_v & ram_data(i);
end loop
b <= b_v;
Click to expand...
Of course, I should point out the timing results for that will be
horrible. But as long as your clock is slow enough...
 
what kind of variable is b_v? i've already compiled the code with that
included, but still to be sure...
 
the compiler complains that the expression:
b_v := ram_data(1) have 18 elements but must have 3456....
 
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