Is there a way in Verilog to refer to a slice of an array?...

[Kevin Simonson]

I\'ve got two Verilog modules that look like this:

module queue
( output [ 64:0] dataOut
, input reset
, input shift
, input [ 64:0] dataIn);
....
endmodule

and

module lessThan
( output lssThn
, input [ 48:0] leftOp
, input [ 48:0] rightOp);
....
endmodule

I\'ve got six instances of module (queue) and need to pipe the forty-nine most significant bits of the output of each of two (queue)s to the two inputs of (lessThan). Is there a way to refer to that forty-nine-bit slice? Or do I have to do something like this:

module hmm ();

wire rs, shLf, shRg;
wire lfOut [ 64:0], lfIn [ 64:0];
wire rgOut [ 64:0], rgIn [ 64:0];
wire rgMsbs [ 48:0], lfMsbs [ 48:0];

queue lfq( lfOut, rs, shLf, lfIn);
queue rgq( rgOut, rs, shRg, rgIn);

lessThan lfLtRg( result, lfMsbs, rgMsbs);

generate
for (bit = 0; bit <= 48; bit = bit + 1)
begin
assign lfMsbs[ bit] = lfOut[ bit + 16];
assign rgMsbs[ bit] = rgOut[ bit + 16];
end
endgenerate

endmodule