Is there a verilog syntax beginning with '$'?

[Robert Willy]

Hi, everyone:
Verilog is not my daily design tool, but it is required a general familiarity
in a job interview. I once noticed a verilog syntax beginning with '$'. I had
found online forum discussing about it, but I can't remember the detail syntax
now.

Could you verilog expert tell me such a usage ('$____')?


Thanks,

 

[Robert Willy]

On Saturday, September 29, 2018 at 3:34:31 PM UTC-5, Robert Willy wrote:

Hi, everyone:
Verilog is not my daily design tool, but it is required a general familiarity
in a job interview. I once noticed a verilog syntax beginning with '$'. I had
found online forum discussing about it, but I can't remember the detail syntax
now.

Could you verilog expert tell me such a usage ('$____')?


Thanks,

Surely, it is not about $display, $write etc. It is a not usual usage, but I
want to know it now.

 

[Robert Willy]

On Saturday, September 29, 2018 at 3:34:31 PM UTC-5, Robert Willy wrote:

Hi, everyone:
Verilog is not my daily design tool, but it is required a general familiarity
in a job interview. I once noticed a verilog syntax beginning with '$'. I had
found online forum discussing about it, but I can't remember the detail syntax
now.

Could you verilog expert tell me such a usage ('$____')?


Thanks,

I got it. It is $signed. Thanks.