Is there a usual way to generate one clock from another?

[benn]

I have a 25Mhz clock that I wish to divide down to around 1.5Mhz..

I tried looking for examples, but it seems they all use PLLs! Is
something like this the way its normally done:

wire oClk_1p5MHz;
reg [16:0] Counter;

always@ (posedge iClk_25Mhz)
begin
Counter <= Counter + 1'b1;
End


assign oClk_1p5MHz = Counter[3]; // Counter[0] = Input/2, Counter[1]
= Input/4, Counter[2]/8; Counter[3]/16


Is this normally considered the preferred (safe) method, or will this
blow up when things wrap around?

 

[Mike Treseler]

benn wrote:

I have a 25Mhz clock that I wish to divide down to around 1.5Mhz..

I would use a larger counter and a larger increment constant.
Read up on phase accumulators.

-- Mike Treseler

 

[gabor]

On Jul 26, 10:24 am, Mike Treseler <mtrese...@gmail.com> wrote:

benn wrote:
I have a 25Mhz clock that I wish to divide down to around 1.5Mhz..

I would use a larger counter and a larger increment constant.
Read up on phase accumulators.

-- Mike Treseler

If the OP only wanted "around" 1.5 MHz, the code posted
should work fine. What you need to avoid is gating the
outputs of the counter. Using any single bit of a
counter will not have glitches. If you need a function
of the counter bits, the best bet is to register
the function with the input clock and define the function
accordingly if the extra clock of latency matters.

For example if you wnated to divide your clock by 18 but
have a 50% duty cycle, you could not just use the MSB
of the counter. Your logic would necessarily be a function
of more than one bit (unless you use non-binary coding or
two counters). In that case you would want to run the
combinatorial function through another flip-flop before
using it as a clock.

By the way, I'm surprised that Mike didn't give his usual
spiel about not using multiple clocks and just creating a
clock enable at 1.5 MHz instead...

 

[Mike Treseler]

gabor wrote:

By the way, I'm surprised that Mike didn't give his usual
spiel about not using multiple clocks and just creating a
clock enable at 1.5 MHz instead...

I've seen the light.
Those who haven't been bitten yet
will disregard such advice because there is no problem.
Those who have been bitten, don't need the advice.

-- Mike Treseler

 

[Mark McDougall]

Mike Treseler wrote:

I've seen the light.
Those who haven't been bitten yet
will disregard such advice because there is no problem.
Those who have been bitten, don't need the advice.

IOW, Got to be cruel to be kind eh Mike?

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

 

[tiwari]

On Jul 26, 3:56 am, benn <benn...@hotmail.com> wrote:

I have a 25Mhz clock that I wish to divide down to around 1.5Mhz..

I tried looking for examples, but it seems they all use PLLs!     Is
something like this the way its normally done:

wire oClk_1p5MHz;
reg [16:0] Counter;

always@ (posedge iClk_25Mhz)
begin
        Counter <= Counter + 1'b1;
End

assign  oClk_1p5MHz = Counter[3]; // Counter[0] = Input/2, Counter[1]
= Input/4, Counter[2]/8; Counter[3]/16

Is this normally considered the preferred (safe) method, or will this
blow up when things wrap around?

Actually, this method will not generate a accurate 1.5Mhz clock. For
exact 1.5MHz clk, first you have have to generate a 75Mhz clk from
25mhz clk and then divide 75MHz clock by 50 to get exact 1.5MHz clock.