Is there a Single simulation n synthesis code for Flip-Flop?

[Viji]

I have a Flip-Flop RTL code

always @ (posedge QCK or posedge QR or posedge QS)
if (QR)
QZ = 1'b0;
else if (QS)
QZ = 1'b1;
else if(QEN)
QZ = QZI;

when simulated has the following issue:

QRT=1 and QST =1 the output QZ->0, the transition of QZ->0 takes place
immediately.
But when QRT changes from 1 ->0 and QST is till '1' the transition from
QZ-> is not immediate it takes place in the next rising edge of the
CLK.

To overcome these I have seperate simulation model for flip-flop

always @(posedge QCK)
if(~QR && ~QS)
if(QEN)
QZ = QZI;
always @(QRor QS)
if(QR)
QZ = 1'b0;
else if (QS)
QZ = 1'b1;

1) Is there anyway to have single RTL code and Simulation Code?
2) How is these issue take care by FPGA vendors like Xilinx ,Altera n
other FPGA vendors?

 

[gabor]

Viji wrote:

I have a Flip-Flop RTL code

always @ (posedge QCK or posedge QR or posedge QS)
if (QR)
QZ = 1'b0;
else if (QS)
QZ = 1'b1;
else if(QEN)
QZ = QZI;

when simulated has the following issue:

QRT=1 and QST =1 the output QZ->0, the transition of QZ->0 takes place
immediately.
But when QRT changes from 1 ->0 and QST is till '1' the transition from
QZ-> is not immediate it takes place in the next rising edge of the
CLK.

To overcome these I have seperate simulation model for flip-flop

always @(posedge QCK)
if(~QR && ~QS)
if(QEN)
QZ = QZI;
always @(QRor QS)
if(QR)
QZ = 1'b0;
else if (QS)
QZ = 1'b1;

1) Is there anyway to have single RTL code and Simulation Code?
2) How is these issue take care by FPGA vendors like Xilinx ,Altera n
other FPGA vendors?

I can answer the second question for Xilinx. It isn't taken care of if
you infer the flip-flop. The inference code suggested in the libraries
guide is the same as yours. Look in the libraries guide under design
element FDCPE and you find:

Verilog Inference Code

always @ (posedge CLR or posedge PRE or posedge C) begin
if (CLR)
Q <= 0;
else if (PRE)
Q <= 1;
else if (CE)
Q <= D;
end

It is possible to instantiate the FDCPE in these tools instead of
inferring. Then of course the synthesis uses the primitives from
its library and the simulator takes source from the unisims
library, so there isn't really a single verilog source that handles
both cases. By the ay the unisims library source has pretty
much the same code you used for simulation, with the addition
of the initialization code for "Global set and reset". So if you
instantiate the flip-flop it should simulate correctly.

 

Viji wrote:

1) Is there anyway to have single RTL code and Simulation Code?

I don't believe it is possible to write an RTL model for a flip-flop
with both asynchronous preset and clear that works correctly for
simulation, if you have to follow the synthesis requirement to use a
single always block.

 

[Enchanter]

First, I think you should image the physical circuit. you use the
posedge to trigger this always.
So only the QX signals change from 0->1 can make always execute.



Viji 写道：

I have a Flip-Flop RTL code

always @ (posedge QCK or posedge QR or posedge QS)
if (QR)
QZ = 1'b0;
else if (QS)
QZ = 1'b1;
else if(QEN)
QZ = QZI;

when simulated has the following issue:

QRT=1 and QST =1 the output QZ->0, the transition of QZ->0 takes place
immediately.
But when QRT changes from 1 ->0 and QST is till '1' the transition from
QZ-> is not immediate it takes place in the next rising edge of the
CLK.

To overcome these I have seperate simulation model for flip-flop

always @(posedge QCK)
if(~QR && ~QS)
if(QEN)
QZ = QZI;
always @(QRor QS)
if(QR)
QZ = 1'b0;
else if (QS)
QZ = 1'b1;

1) Is there anyway to have single RTL code and Simulation Code?
2) How is these issue take care by FPGA vendors like Xilinx ,Altera n
other FPGA vendors?