L
leon
Guest
Hi,
One of the limitiations of verilog syntehsis tools is the inablity to
support hierarchical inferences. For example if I were to declare a
function in modules and have that synthesized then I should be able to
refer to the function by giving it a path using the module instance
name. This is supported by simulation tools and would be a great
alternative to not having packages as in VHDL.
This will also eliminate the need for annoying include files or
creating a module for each function and instantiating it (which is a
dumb approach for this purpose).
Here is a piece of code that works with simulations - anybody know of
any synthesis tools that support this - synplify, synopsys, RC, Magma
etc.....
Thanks
module arith();
function [3:0] add;
input [3:0] a;
input [3:0] b;
begin:add_func
add = a + b;
end
endfunction
endmodule
module test(
input [3:0] a,
input [3:0] b,
output wire [3:0] add
);
arith arith();
assign add = arith.add(a,b);
endmodule
One of the limitiations of verilog syntehsis tools is the inablity to
support hierarchical inferences. For example if I were to declare a
function in modules and have that synthesized then I should be able to
refer to the function by giving it a path using the module instance
name. This is supported by simulation tools and would be a great
alternative to not having packages as in VHDL.
This will also eliminate the need for annoying include files or
creating a module for each function and instantiating it (which is a
dumb approach for this purpose).
Here is a piece of code that works with simulations - anybody know of
any synthesis tools that support this - synplify, synopsys, RC, Magma
etc.....
Thanks
module arith();
function [3:0] add;
input [3:0] a;
input [3:0] b;
begin:add_func
add = a + b;
end
endfunction
endmodule
module test(
input [3:0] a,
input [3:0] b,
output wire [3:0] add
);
arith arith();
assign add = arith.add(a,b);
endmodule