Is there a concatention operator on the Left Hand Side of '=

R

Raban

Guest
I am reading something from the Altera website example.

http://vader.ece.ucsb.edu/digilab-fpga/pdfs/Quartus-Verilog-tutorial.pdf


Around pages 10-12 there is are 3 modules with the last one as follows:

// k-bit adder
module adderk (carryin, X, Y, S, carryout);
parameter k = 8;
input [k?1:0] X, Y;
input carryin;
output [k?1:0] S;
output carryout;
reg [k?1:0] S;
reg carryout;
always @(X or Y or carryin)
{carryout, S} = X + Y + carryin;
endmodule



what I am not clear on is the last line:

{carryout, S} = X + Y + carryin;

What are the Curly Braces on the Left Hand Side of the Equal Sign doing
here?
Is it Concatention? or is it Add then Assignment? Or Multiple Assignment?

Looking at the logic circuit on page 10 gives me some idea, but I am not
100% sure.

Not sure how the outputs look to the world outside the module

I know the use of Curly Braces on the Right Hand side is Concatenation, but
not the Left hand side.

Looked at a Verilog book but nothing like that or on Google Search.

Any help would be appreciated? Thanks.
 
So, on the left hand side, what comes first? are they concatenated first and
then assigned as a some new combo product. Or is carryout and S each
assigned X + Y + carryin and then carryout and S are then concatenated? or
the other way around?

coming from a C# background, I only see a variable on the left.

here in verilog, I am not sure what is really going on.

Is seems like in the left hand side, carryout and S are first concatenated
and then you have some result of which I have no idea where that result will
be assigned outside the module.

Very confusing what is going on and which order things are happening in. and
for what purpose




"John Rible" <news@sandpipers.com> wrote in message
news:g0t7oc02ueh@news2.newsguy.com...
Concatenation works on both sides of assignments

Raban wrote:
I am reading something from the Altera website example.

http://vader.ece.ucsb.edu/digilab-fpga/pdfs/Quartus-Verilog-tutorial.pdf


Around pages 10-12 there is are 3 modules with the last one as follows:

// k-bit adder
module adderk (carryin, X, Y, S, carryout);
parameter k = 8;
input [k?1:0] X, Y;
input carryin;
output [k?1:0] S;
output carryout;
reg [k?1:0] S;
reg carryout;
always @(X or Y or carryin)
{carryout, S} = X + Y + carryin;
endmodule



what I am not clear on is the last line:

{carryout, S} = X + Y + carryin;

What are the Curly Braces on the Left Hand Side of the Equal Sign doing
here?
Is it Concatention? or is it Add then Assignment? Or Multiple Assignment?

Looking at the logic circuit on page 10 gives me some idea, but I am not
100% sure.

Not sure how the outputs look to the world outside the module

I know the use of Curly Braces on the Right Hand side is Concatenation,
but not the Left hand side.

Looked at a Verilog book but nothing like that or on Google Search.

Any help would be appreciated? Thanks.
Click to expand...
 
Concatenation works on both sides of assignments

Raban wrote:
I am reading something from the Altera website example.

http://vader.ece.ucsb.edu/digilab-fpga/pdfs/Quartus-Verilog-tutorial.pdf


Around pages 10-12 there is are 3 modules with the last one as follows:

// k-bit adder
module adderk (carryin, X, Y, S, carryout);
parameter k = 8;
input [k?1:0] X, Y;
input carryin;
output [k?1:0] S;
output carryout;
reg [k?1:0] S;
reg carryout;
always @(X or Y or carryin)
{carryout, S} = X + Y + carryin;
endmodule



what I am not clear on is the last line:

{carryout, S} = X + Y + carryin;

What are the Curly Braces on the Left Hand Side of the Equal Sign doing
here?
Is it Concatention? or is it Add then Assignment? Or Multiple Assignment?

Looking at the logic circuit on page 10 gives me some idea, but I am not
100% sure.

Not sure how the outputs look to the world outside the module

I know the use of Curly Braces on the Right Hand side is Concatenation, but
not the Left hand side.

Looked at a Verilog book but nothing like that or on Google Search.

Any help would be appreciated? Thanks.
Click to expand...
 
On Mon, 19 May 2008 21:31:27 -0500, "Raban" <or09uus@hotmail.com>
wrote:

So, on the left hand side, what comes first? are they concatenated first and
then assigned as a some new combo product. Or is carryout and S each
assigned X + Y + carryin and then carryout and S are then concatenated? or
the other way around?

coming from a C# background, I only see a variable on the left.

here in verilog, I am not sure what is really going on.

Is seems like in the left hand side, carryout and S are first concatenated
and then you have some result of which I have no idea where that result will
be assigned outside the module.

Very confusing what is going on and which order things are happening in. and
for what purpose

{carryout, S} = X + Y + carryin;
Click to expand...
It's the former. You need to think of these as vectors of bits. A K
bit adder as in your example can generate a K+1 bit output which is
the size of the vector you need to assign the result in Verilog lest
you get a truncation. So by concatenating the left hand side you have
a K+1 long vector which has exactly the size needed to write
X+Y+carryin.
 
Raban wrote:
I am reading something from the Altera website example.

http://vader.ece.ucsb.edu/digilab-fpga/pdfs/Quartus-Verilog-tutorial.pdf


Around pages 10-12 there is are 3 modules with the last one as follows:

// k-bit adder
module adderk (carryin, X, Y, S, carryout);
parameter k = 8;
input [k?1:0] X, Y;
input carryin;
output [k?1:0] S;
output carryout;
reg [k?1:0] S;
reg carryout;
always @(X or Y or carryin)
{carryout, S} = X + Y + carryin;
endmodule
Click to expand...
I'm more confused about the register widths [k?1:0]. Is that a typo?
It doesn't make sense as the if-then-else operator. It seems to make
more sense if it is [k-1:0].

You can think about the concatenation as the characteristically
Verilog-style less-verbose version of the following code, which uses an
intermediate variable, but synthesizes identically:

input [k-1:0] X,Y;
input carryin;
output [k-1:0] S;
output carryout;
reg [k:0] intermediate;
always@(X, Y, carryin)
begin
intermediate = X+Y+carryin;
carryout = intermediate[k];
S = intermediate[k-1:0];
end

-Kevin
 
On May 19, 8:28 pm, "Raban" <or09...@hotmail.com> wrote:
what I am not clear on is the last line:

  {carryout, S} = X + Y + carryin;

What are the Curly Braces on the Left Hand Side of the Equal Sign doing
here?
Is it Concatention? or is it Add then Assignment? Or Multiple Assignment?
Click to expand...
It is an assignment to a concatenation. If the concatenation were on
the right-hand side, the least significant bits would come from S and
the most significant bit would come from carryout. When it is on the
left-hand side, the least significant bits are written to S, and the
most significant bit is written to carryout. In both cases, it acts
like carryout is an extra bit just above the uppermost bit of S.
 
On May 20, 11:53 am, Kevin Neilson
<kevin_neil...@removethiscomcast.net> wrote:
Raban wrote:
I am reading something from the Altera website example.

http://vader.ece.ucsb.edu/digilab-fpga/pdfs/Quartus-Verilog-tutorial.pdf

Around pages 10-12 there is are 3 modules with the last one as follows:

// k-bit adder
module adderk (carryin, X, Y, S, carryout);
parameter k = 8;
input [k?1:0] X, Y;
input carryin;
output [k?1:0] S;
output carryout;
reg [k?1:0] S;
reg carryout;
always @(X or Y or carryin)
{carryout, S} = X + Y + carryin;
endmodule

I'm more confused about the register widths [k?1:0]. Is that a typo?
It doesn't make sense as the if-then-else operator. It seems to make
more sense if it is [k-1:0].
Click to expand...
It almost undoubtedly is [k-1:0]. This sort of "typo"
is usually computer generated. In this case the minus
sign has probably been converting to some non-ASCII
character like an em dash, then the conversion to
PDF picked a font that didn't support this character
and very handily replaced it with "?".

It is even possible that the people publishing the
datasheet don't see the "?" when they open the
document because somewhere in their environment
is the original font with the em dash...

Gotta love computers...

Cheers,
Gabor
 
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