Is there a concatention operator on the Left Hand Side of '=

[Raban]

I am reading something from the Altera website example.

http://vader.ece.ucsb.edu/digilab-fpga/pdfs/Quartus-Verilog-tutorial.pdf


Around pages 10-12 there is are 3 modules with the last one as follows:

// k-bit adder
module adderk (carryin, X, Y, S, carryout);
parameter k = 8;
input [k?1:0] X, Y;
input carryin;
output [k?1:0] S;
output carryout;
reg [k?1:0] S;
reg carryout;
always @(X or Y or carryin)
{carryout, S} = X + Y + carryin;
endmodule



what I am not clear on is the last line:

{carryout, S} = X + Y + carryin;

What are the Curly Braces on the Left Hand Side of the Equal Sign doing
here?
Is it Concatention? or is it Add then Assignment? Or Multiple Assignment?

Looking at the logic circuit on page 10 gives me some idea, but I am not
100% sure.

Not sure how the outputs look to the world outside the module

I know the use of Curly Braces on the Right Hand side is Concatenation, but
not the Left hand side.

Looked at a Verilog book but nothing like that or on Google Search.

Any help would be appreciated? Thanks.