Is there a better coding style for this testbench?

[Robert Willy]

Hi,

I have the following test bench lines from Matlab hdl coder generated.
Although it works, I feel a little uneasy for the lengthy (5000 lines for
each input and expected test vectors when I read it. I would like to
know whether verilog experts use a different style in their coding.


Do you put the data in a separate file and read it from there?
Do you have a short example show me that?


Thanks,





// **************************************
initial //Input & Output data
begin

// Input data for alpha_Quantizer_out1
alpha_out1_0_force[ 0] <= 3'h7;
alpha_out1_0_force[ 1] <= 3'h7;
....



alpha_out1_0_force[5000] <= 3'h1;

// Output data for Out
Out_expected[ 0] <= 1'h0;
Out_expected[ 1] <= 1'h0;
....

Out_expected[5000] <= 1'h0;

 

[Robert Willy]

On Sunday, March 15, 2015 at 4:30:54 AM UTC-7, Robert Willy wrote:

Hi,

I have the following test bench lines from Matlab hdl coder generated.
Although it works, I feel a little uneasy for the lengthy (5000 lines for
each input and expected test vectors when I read it. I would like to
know whether verilog experts use a different style in their coding.


Do you put the data in a separate file and read it from there?
Do you have a short example show me that?


Thanks,





// **************************************
initial //Input & Output data
begin

// Input data for alpha_Quantizer_out1
alpha_out1_0_force[ 0] <= 3'h7;
alpha_out1_0_force[ 1] <= 3'h7;
...



alpha_out1_0_force[5000] <= 3'h1;

// Output data for Out
Out_expected[ 0] <= 1'h0;
Out_expected[ 1] <= 1'h0;
...

Out_expected[5000] <= 1'h0;

I see the following snippet from a web, but it has compiling error:

near "signed": syntax error, unexpected signed, expecting IDENTIFIER or TYPE_IDENTIFIER

of the third line ("logic signed [21:0] captured_data;").
.................
integer data_file ; // file handler
integer scan_file ; // file handler
logic signed [21:0] captured_data;
`define NULL 0

initial begin
data_file = $fopen("data_file.dat", "r");
if (data_file == `NULL) begin
$display("data_file handle was NULL");
$finish;
end
end

always @(posedge clk) begin
scan_file = $fscanf(data_file, "%d\n", captured_data);
if (!$feof(data_file)) begin
//use captured_data as you would any other wire or reg value;
end
end

..............

The third line is not a real line, but a descriptive comment line? Could you
tell me that?

Thanks,

 

[GaborSzakacs]

Robert Willy wrote:

On Sunday, March 15, 2015 at 4:30:54 AM UTC-7, Robert Willy wrote:
Hi,

I have the following test bench lines from Matlab hdl coder generated.
Although it works, I feel a little uneasy for the lengthy (5000 lines for
each input and expected test vectors when I read it. I would like to
know whether verilog experts use a different style in their coding.


Do you put the data in a separate file and read it from there?
Do you have a short example show me that?


Thanks,





// **************************************
initial //Input & Output data
begin

// Input data for alpha_Quantizer_out1
alpha_out1_0_force[ 0] <= 3'h7;
alpha_out1_0_force[ 1] <= 3'h7;
...



alpha_out1_0_force[5000] <= 3'h1;

// Output data for Out
Out_expected[ 0] <= 1'h0;
Out_expected[ 1] <= 1'h0;
...

Out_expected[5000] <= 1'h0;

I see the following snippet from a web, but it has compiling error:

near "signed": syntax error, unexpected signed, expecting IDENTIFIER or TYPE_IDENTIFIER

of the third line ("logic signed [21:0] captured_data;").
.................
integer data_file ; // file handler
integer scan_file ; // file handler
logic signed [21:0] captured_data;
`define NULL 0

initial begin
data_file = $fopen("data_file.dat", "r");
if (data_file == `NULL) begin
$display("data_file handle was NULL");
$finish;
end
end

always @(posedge clk) begin
scan_file = $fscanf(data_file, "%d\n", captured_data);
if (!$feof(data_file)) begin
//use captured_data as you would any other wire or reg value;
end
end

..............

The third line is not a real line, but a descriptive comment line? Could you
tell me that?

Thanks,

If you're not using System Verilog, you need to change "logic" to "reg"
to get that line to compile. "logic" is a new construct for System
Verilog that can be used interchangeably as a wire or reg. It more
resembles a signal in VHDL in that it can be assigned in a process or
in a continuous assignment (or for simulation possibly both).

Hmmm... I think $fscanf may also have been introduced in System
Verilog. You might find that you get an error from that line if
you fix the first problem.

--
Gabor