Is the following a correct usage in System Verilog

[parag]

interface SyncBus (input bit clk);
wire a,b,c;
endinterface
typedef virtual SyncBus VI;

module top;
bit clk;
SyncBus b1 (clk);
SyncBus b2(clk);
VI v[2] = '{b1,b2};
endmodule