Long answer: Within the next few months, the SystemVerilog and
Verilog language standards will merge into a single standard,
so it makes even more sense to expose your SV questions here.
And in any case, the more people get to see what SV can do
for them (and it's plenty), the more likely they will be to
demand appropriate SV language support from their tool vendors.
The mainstream big-$$$$$ simulator and synthesis vendors already
offer superb SV support, but the support in certain well-known
integrated FPGA tool suites is disappointingly absent.
--
Jonathan Bromley
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