Is PLI synthesizable?

V

Verictor

Guest
Hi,

After a conversation, I wonder if Verilog PLI's synthesiszble or not?
Even though it is well understood that PLI is mainly for verification
purpose, but things may have changed. Any news?

Thanks
 
On Mar 22, 6:02 pm, "Verictor" <stehu...@gmail.com> wrote:
[...]
After a conversation, I wonder if Verilog PLI's synthesiszble or not?
Even though it is well understood that PLI is mainly for verification
purpose, but things may have changed. Any news?
[...]
Click to expand...

What benefit do you expect from a synthesizable Verilog PLI that you
cannot get from the current language?

Cheers,

Guenter
 
On Mar 22, 11:48 am, "Guenter" <GHEDWHCVE...@spammotel.com> wrote:
On Mar 22, 6:02 pm, "Verictor" <stehu...@gmail.com> wrote:
[...]> After a conversation, I wonder if Verilog PLI's synthesiszble or not?
Even though it is well understood that PLI is mainly for verification
purpose, but things may have changed. Any news?

[...]

What benefit do you expect from a synthesizable Verilog PLI that you
cannot get from the current language?

Cheers,

Guenter
Click to expand...
 
On Mar 22, 11:48 am, "Guenter" <GHEDWHCVE...@spammotel.com> wrote:
On Mar 22, 6:02 pm, "Verictor" <stehu...@gmail.com> wrote:
[...]> After a conversation, I wonder if Verilog PLI's synthesiszble or not?
Even though it is well understood that PLI is mainly for verification
purpose, but things may have changed. Any news?

[...]

What benefit do you expect from a synthesizable Verilog PLI that you
cannot get from the current language?

Cheers,

Guenter
Click to expand...
Well, there are many answers to your question. The most simple way
would be a counter-question: does a synthesizable PLI eliminate
intermediate tools (and languages)? The "current" language is also
evloving drastically. Why not PLI?

I think my question was not about benefit doing it or not but just
doable or not.

Thanks anyway.
 
On Mar 22, 8:23 pm, "Verictor" <stehu...@gmail.com> wrote:
On Mar 22, 11:48 am, "Guenter" <GHEDWHCVE...@spammotel.com> wrote:
[...]

What benefit do you expect from a synthesizable Verilog PLI that you
cannot get from the current language?

Cheers,

Guenter

Well, there are many answers to your question. The most simple way
would be a counter-question: does a synthesizable PLI eliminate
intermediate tools (and languages)? The "current" language is also
evloving drastically. Why not PLI?
Click to expand...
Maybe you could elaborate on what the Verilog PLI in its current state
is in your eyes and how you would want it to evolve that it works
together with a synthesis tool?

I think my question was not about benefit doing it or not but just
doable or not.
Click to expand...
But for some reason you have a motivation for that change that brings
you in first place to the idea about changing it. I guess your answer
to that is your above counter question. Now my question is, what is
your point? Do you want to change the Verilog PLI for the sake of
changing it or do you want to improve a synthesis tool?
 
On Mar 23, 1:23 pm, "Guenter" <GHEDWHCVE...@spammotel.com> wrote:
On Mar 22, 8:23 pm, "Verictor" <stehu...@gmail.com> wrote:

On Mar 22, 11:48 am, "Guenter" <GHEDWHCVE...@spammotel.com> wrote:
[...]

What benefit do you expect from a synthesizable Verilog PLI that you
cannot get from the current language?

Cheers,

Guenter

Well, there are many answers to your question. The most simple way
would be a counter-question: does a synthesizable PLI eliminate
intermediate tools (and languages)? The "current" language is also
evloving drastically. Why not PLI?

Maybe you could elaborate on what the Verilog PLI in its current state
is in your eyes and how you would want it to evolve that it works
together with a synthesis tool?

I think my question was not about benefit doing it or not but just
doable or not.

But for some reason you have a motivation for that change that brings
you in first place to the idea about changing it. I guess your answer
to that is your above counter question. Now my question is, what is
your point? Do you want to change the Verilog PLI for the sake of
changing it or do you want to improve a synthesis tool?
Click to expand...


How can somebody define new structural constructs using PLI. to an
extent we can never do away with the main simulator. And I think that
it is now possible to atleast add callbacks and other behaviorial
constructs using PLI.
But how is it possible for PLI to replace languages like verilog and
VHDL which bring in so much
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top