Is it possible to split a range definition?

[Michael]

Is it possible to create a subtype with a range that is split over two
different areas?

for example:

SUBTYPE hex IS character RANGE('0' to '9' & 'A' to 'F');

 

[fabbl]

Try it

"Michael" <nospam@thanks.com> wrote in message
news:gLCLc.4$f12.2@dfw-service2.ext.ray.com...

Is it possible to create a subtype with a range that is split over two
different areas?

for example:

SUBTYPE hex IS character RANGE('0' to '9' & 'A' to 'F');

 

[Michael]

fabbl wrote:

Try it

"Michael" <nospam@thanks.com> wrote in message
news:gLCLc.4$f12.2@dfw-service2.ext.ray.com...

Is it possible to create a subtype with a range that is split over two
different areas?

for example:

SUBTYPE hex IS character RANGE('0' to '9' & 'A' to 'F');

Do you think I would be posting here if I hadn't already tried it?

I've looked through The Designers Guide, searched around the net, and a
number of FAQ's, still, I haven't found anything that says how to do it.
I also haven't found anything that leaves me with the impression that
it can't be done either.

Does anyone out there have any useful feedback?

 

[Jonathan Bromley]

On Thu, 22 Jul 2004 10:34:48 -0700, Michael <nospam@thanks.com> wrote:

"Michael" <nospam@thanks.com> wrote in message
news:gLCLc.4$f12.2@dfw-service2.ext.ray.com...

Is it possible to create a subtype with a range that is
split over twodifferent areas?

for example:
SUBTYPE hex IS character RANGE('0' to '9' & 'A' to 'F');

No, VHDL doesn't offer disjoint ranges.

Pascal and Modula-xxx offer sets, which get you some of what
I suspect you want. Too bad they didn't make it into VHDL.

'e' (Verisity's verification language) has disjoint ranges for
subtypes. Vera may have such a thing too, but I don't know.

For some purposes it's cool to create a set lookalike in VHDL...

type t_charset is array(character) of boolean;

and then you can mess around creating sets from aggregates:

constant hex_digit: t_charset := (
'0' to '9' => TRUE,
'A' to 'F' => TRUE,
others => FALSE );

With a bit more work you could overload "and", "or" and
other operators to mimic the usual set operations.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.