T
Test01
Guest
Can Xilinx or Altera FPGA support scan feature to save the state? Any
details will be great.
details will be great.
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P
Phil Everett
Guest
"Test01" <cpandya@yahoo.com> wrote in message
news:16087c47-a88a-454a-b55a-11097c206490@q30g2000yqj.googlegroups.com...
news:16087c47-a88a-454a-b55a-11097c206490@q30g2000yqj.googlegroups.com...
Assuming you are not using PLL's - stop the clockCan Xilinx or Altera FPGA support scan feature to save the state? Any
details will be great.
T
Test01
Guest
On Dec 2, 12:08 pm, "Phil Everett" <ph...@hotnots.rot> wrote:
and then restore the state at some other time. Thus I need to store
the fpga state in flash storage device. I was curious if the JTAG
tool that comes with the FPGA software will provide such capability.
But I need the ability save the state then power off the fpga board"Test01" <cpan...@yahoo.com> wrote in message
news:16087c47-a88a-454a-b55a-11097c206490@q30g2000yqj.googlegroups.com...
Can Xilinx or Altera FPGA support scan feature to save the state? Any
details will be great.
Assuming you are not using PLL's - stop the clock
and then restore the state at some other time. Thus I need to store
the fpga state in flash storage device. I was curious if the JTAG
tool that comes with the FPGA software will provide such capability.
K
Kolja Sulimma
Guest
On 2 Dez., 21:07, Test01 <cpan...@yahoo.com> wrote:
newer xilinx part
can read out flop-flop state via the configuration port if the design
suports this. (Readback Capture)
I am not sure, but I believe that BRAM content can't be read out this
way, so you need even more application
support, such as making sure that FIFOs are emptied, caches are
invalided and other RAMs are read out by
the application before powering down.
I guess it can be done without any principal problems but will be very
challenging in practice.
Regards,
Kolja Sulimma
cronologic
As far as I know there no ready to use tools that support this, butOn Dec 2, 12:08 pm, "Phil Everett" <ph...@hotnots.rot> wrote:
"Test01" <cpan...@yahoo.com> wrote in message
news:16087c47-a88a-454a-b55a-11097c206490@q30g2000yqj.googlegroups.com....
Can Xilinx or Altera FPGA support scan feature to save the state? Any
details will be great.
Assuming you are not using PLL's - stop the clock
But I need the ability save the state then power off the fpga board
and then restore the state at some other time. Thus I need to store
the fpga state in flash storage device. I was curious if the JTAG
tool that comes with the FPGA software will provide such capability.
newer xilinx part
can read out flop-flop state via the configuration port if the design
suports this. (Readback Capture)
I am not sure, but I believe that BRAM content can't be read out this
way, so you need even more application
support, such as making sure that FIFOs are emptied, caches are
invalided and other RAMs are read out by
the application before powering down.
I guess it can be done without any principal problems but will be very
challenging in practice.
Regards,
Kolja Sulimma
cronologic
B
backhus
Guest
On 2 Dez., 21:07, Test01 <cpan...@yahoo.com> wrote:
early Xilinx FPGA Families (X3000) had a power down feature with
battery backup.
thus the State of the FPGA is saved in itself when powering off the
board.
Since todays FPGAs are also SRAM based, it might still be possible to
to do something like that.
Have a nice synthesis
Eilert
Hi,On Dec 2, 12:08 pm, "Phil Everett" <ph...@hotnots.rot> wrote:
"Test01" <cpan...@yahoo.com> wrote in message
news:16087c47-a88a-454a-b55a-11097c206490@q30g2000yqj.googlegroups.com....
Can Xilinx or Altera FPGA support scan feature to save the state? Any
details will be great.
Assuming you are not using PLL's - stop the clock
But I need the ability save the state then power off the fpga board
and then restore the state at some other time. Thus I need to store
the fpga state in flash storage device. I was curious if the JTAG
tool that comes with the FPGA software will provide such capability.
early Xilinx FPGA Families (X3000) had a power down feature with
battery backup.
thus the State of the FPGA is saved in itself when powering off the
board.
Since todays FPGAs are also SRAM based, it might still be possible to
to do something like that.
Have a nice synthesis
Eilert
J
Jan Coombs
Guest
On 05/12/11 06:20, backhus wrote:
close to zero power.
Jan Coombs
Actel Igloo have a pin to freeze operation and maintain state atOn 2 Dez., 21:07, Test01<cpan...@yahoo.com> wrote:
Can Xilinx or Altera FPGA support scan feature to save the state? Any
details will be great.
early Xilinx FPGA Families (X3000) had a power down feature with
battery backup.
thus the State of the FPGA is saved in itself when powering off the
board.
Since todays FPGAs are also SRAM based, it might still be possible to
to do something like that.
close to zero power.
Jan Coombs
A
Andy
Guest
IIRC, the ram (block and distributed) data are part of the
configuration stream. So, if your FPGA logic can store and retrieve
its state to block rams, all you have to do is store the state to
block ram and read back the configuration. Then use that configuration
(instead of the normal one) when you power back up. Naturally, your
FPGA has to be able to initialize state from rams, which means the
original configuration needs to have the "cold reset" state data for
the rams.
Andy
configuration stream. So, if your FPGA logic can store and retrieve
its state to block rams, all you have to do is store the state to
block ram and read back the configuration. Then use that configuration
(instead of the normal one) when you power back up. Naturally, your
FPGA has to be able to initialize state from rams, which means the
original configuration needs to have the "cold reset" state data for
the rams.
Andy
G
Gabor
Guest
Andy wrote:
block RAM readback uses the same ports as your logic. So you can't
really do it with a running design. If you have a way to freeze the
operation (like de-asserting the global write enable), then presumably
you can do this. There are "startup" blocks on most of the newer
devices that allow you to muck with the global signals, but you might
have other issues, not the least of which is that the global start-up
signals have significant skew over the FPGA fabric, so you might also
need to gate off your clocks. All in all, I think this would be a
pretty ambitious project to get working.
-- Gabor
There was a thread on this topic in the Xilinx forums recently. TheIIRC, the ram (block and distributed) data are part of the
configuration stream. So, if your FPGA logic can store and retrieve
its state to block rams, all you have to do is store the state to
block ram and read back the configuration. Then use that configuration
(instead of the normal one) when you power back up. Naturally, your
FPGA has to be able to initialize state from rams, which means the
original configuration needs to have the "cold reset" state data for
the rams.
Andy
block RAM readback uses the same ports as your logic. So you can't
really do it with a running design. If you have a way to freeze the
operation (like de-asserting the global write enable), then presumably
you can do this. There are "startup" blocks on most of the newer
devices that allow you to muck with the global signals, but you might
have other issues, not the least of which is that the global start-up
signals have significant skew over the FPGA fabric, so you might also
need to gate off your clocks. All in all, I think this would be a
pretty ambitious project to get working.
-- Gabor
A
Andy
Guest
On Dec 5, 4:00 pm, Gabor <ga...@szakacs.invalid> wrote:
recovery) of a design would necessarily have to be taken while the
operational logic was frozen anyway, for the snapshot to have any
coherency.
Given that some portions of the FPGA would have to remain working to
transfer register contents into rams, use of a global clock/write
enable to freeze the design would not be possible. Of course those
portions used for the transfer to/from ram at shutdown/startup would
have to use conventional initialization mechanisms (reset/preset).
There would likely also be external interfaces, etc. that would need
to have special re-initialization behavior to restart communications
with external systems that may or may not have experienced the same
event.
Andy
Excellent points. I took it as granted that a snapshot (to be used forThere was a thread on this topic in the Xilinx forums recently. The
block RAM readback uses the same ports as your logic. So you can't
really do it with a running design. If you have a way to freeze the
operation (like de-asserting the global write enable), then presumably
you can do this. There are "startup" blocks on most of the newer
devices that allow you to muck with the global signals, but you might
have other issues, not the least of which is that the global start-up
signals have significant skew over the FPGA fabric, so you might also
need to gate off your clocks. All in all, I think this would be a
pretty ambitious project to get working.
-- Gabor
recovery) of a design would necessarily have to be taken while the
operational logic was frozen anyway, for the snapshot to have any
coherency.
Given that some portions of the FPGA would have to remain working to
transfer register contents into rams, use of a global clock/write
enable to freeze the design would not be possible. Of course those
portions used for the transfer to/from ram at shutdown/startup would
have to use conventional initialization mechanisms (reset/preset).
There would likely also be external interfaces, etc. that would need
to have special re-initialization behavior to restart communications
with external systems that may or may not have experienced the same
event.
Andy