Is it possible to run Verilog and VHDL combined

Hello guys
i am new VHDL. i have a system fpga code in vhdl and i have a ddr
sdram controller in verilog. is it possible for me combine both these
and synthesize to load in the fpga.
thanks in advance
Subin

 

[Mark McDougall]

subin.82@gmail.com wrote:

i am new VHDL. i have a system fpga code in vhdl and i have a ddr
sdram controller in verilog. is it possible for me combine both these
and synthesize to load in the fpga.

Absolutely!

You need to create a VHDL component description for the sdram
controller. Then you can instantiate it in your VHDL system code.

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266