S
Swarna B
Guest
Is it possible to define a macro through the GUI of ISE or by any
command line
means? I mean, just like we give a +define+MACRO_NAME along with a
verilog
compilation commandline in Modelsim or in NC verilog. How do I do it?
As, otherwise, it becomes quite messy affair of commenting and
uncommenting
lines containing `define in the source code. Xilinx Answer records
don't seem to have anything on this.
Regrds
Swarna
command line
means? I mean, just like we give a +define+MACRO_NAME along with a
verilog
compilation commandline in Modelsim or in NC verilog. How do I do it?
As, otherwise, it becomes quite messy affair of commenting and
uncommenting
lines containing `define in the source code. Xilinx Answer records
don't seem to have anything on this.
Regrds
Swarna