Is it necessary to fully describe logic

[gene]

consider this example:
----------------------------------------
module bob (iReset, iClock, oCount)

input iReset;
input iClock;
output [3:0] oCount;

reg [3:0] oCount;

always @(posedge iReset or posedge iClock)
begin
if (iReset == 1)
oCount <= 0;
else
if (oCount < 4'b1111)
oCount <= oCount + 1;
else
oCount <= oCount;
end

--------------------------------------------

Using XST, it generates a counter and it looks correct. If I remove
the
"else oCount <= oCount" line, it synthesizes exactly the same.

In my VHDL days, I was taught to fully describe the logic so that it
doesn't infer unnecessary latches. In this case, it didn't. Is that a
property of verilog or XST, or am I missing something?

thanks

gene

 

[John_H]

You're explicitly going for a latch-style structure, specifically a
flip-flop.
The issue with presenting all cases is for combinatorial specifications that
would want to default to "stay the same" when there is no definition for its
new condition, resulting in a latch.
For registered logic (posedge iClock) the "else do nothing" state results in
the same thing as including that else x <= x assignment.


"gene" <fazool1_2000@yahoo.com> wrote in message
news:adbf00ac.0405181152.6aab98f7@posting.google.com...

consider this example:
----------------------------------------
module bob (iReset, iClock, oCount)

input iReset;
input iClock;
output [3:0] oCount;

reg [3:0] oCount;

always @(posedge iReset or posedge iClock)
begin
if (iReset == 1)
oCount <= 0;
else
if (oCount < 4'b1111)
oCount <= oCount + 1;
else
oCount <= oCount;
end

--------------------------------------------

Using XST, it generates a counter and it looks correct. If I remove
the
"else oCount <= oCount" line, it synthesizes exactly the same.

In my VHDL days, I was taught to fully describe the logic so that it
doesn't infer unnecessary latches. In this case, it didn't. Is that a
property of verilog or XST, or am I missing something?

thanks

gene

 

[Hardik]

Hello Gene,
You need to fully describe/specify logic only if
you want to describe and synthesize a combinational
logic functional. Counter is a state machine which consist
of state holding flip flops(4 in you case). This will get
synthesized correctly even if you don't include

else
oCount <= oCount;

in your RTL code.
Anyway this is a redundant code because even if
the behaviour is not fully specified , the flip flops will
retain their last state for the conditions ( oCount >= 4'b1111 in your case)
where the behaviour is not specified.

-Hardik

gene wrote:

consider this example:
----------------------------------------
module bob (iReset, iClock, oCount)

input iReset;
input iClock;
output [3:0] oCount;

reg [3:0] oCount;

always @(posedge iReset or posedge iClock)
begin
if (iReset == 1)
oCount <= 0;
else
if (oCount < 4'b1111)
oCount <= oCount + 1;
else
oCount <= oCount;
end

--------------------------------------------

Using XST, it generates a counter and it looks correct. If I remove
the
"else oCount <= oCount" line, it synthesizes exactly the same.

In my VHDL days, I was taught to fully describe the logic so that it
doesn't infer unnecessary latches. In this case, it didn't. Is that a
property of verilog or XST, or am I missing something?

thanks

gene

 

[gene]

thanks for the repies!



gene