Is it incomplete sensitivity list ?

  • Thread starter Mohammed A khader
  • Start date
M

Mohammed A khader

Guest
HI all,

Is it necesary to specify Dec_En and Addrs_En in the following code.
Synplicity it as a Warning.

Thanks for your comments..

Mohammed khader.

Regs:process(Clk)
begin
if(Dec_En = '1' and RISING_EDGE(Clk))then
Decode_Reg <= srl_buff;
end if;
if(Addrs_En = '1' and RISING_EDGE(Clk))then
Addrs_Reg <= std_logic_vector(Decode_Reg(12 downto 6));
end if;
if(Data_En = '1' and RISING_EDGE(Clk))then
Data_Reg <= Decode_Reg;
end if;
end process Regs;
 
HI all,

Is it necesary to specify Dec_En and Addrs_En in the following code.
Synplicity it as a Warning.

Thanks for your comments..

Mohammed khader.

Regs:process(Clk)
begin
if(Dec_En = '1' and RISING_EDGE(Clk))then
Decode_Reg <= srl_buff;
end if;
if(Addrs_En = '1' and RISING_EDGE(Clk))then
Addrs_Reg <= std_logic_vector(Decode_Reg(12 downto 6));
end if;
if(Data_En = '1' and RISING_EDGE(Clk))then
Data_Reg <= Decode_Reg;
end if;
end process Regs;


In all conditions I see rising_edge(clk). So when there no rising_edge
nothing is changed.
So I don't see a reason adding other signals. The following description is
the same:

process(clk)
begin
if rising_edge(clk) then
if dec_en='1' then Decode_Reg <= srl_buff; end if;
if addrs_en='1' then Addrs_Reg <= std_logic_vector(Decode_Reg(12 downto
6)); end if;
if data_en='1' then Data_Reg <= Decode_Reg; end if;
end if;
end process;

Egbert Molenkamp
Click to expand...
I'm not very sure but I think that the correct way to implement a
synthesisable clocked process is using the "if rising_edge(clk) then"
structure. Though in simulation it is exactly the same of course. It's
all just how your tool is interpreting the code you've written.
 
Mohammed,
What Egbert has proposed will work well in nearly
all synthesis tools.

What you coded, while simulation wise is correct
and is compliant with 1076.6-2004 (the VHDL RTL Synthesis
Specification) I would not be surprised to find that
some vendors do not fully support it yet.

To get them to fully support it, I would turn in your
code as a but and indicate to them that the code is
1076.6-2004 compliant.

Cheers,
Jim Lewis
vice-chair 1076.6 working group
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


"Mohammed A khader" <am.imak@gmail.com> wrote in message
news:1109770017.670742.36360@o13g2000cwo.googlegroups.com...

HI all,

Is it necesary to specify Dec_En and Addrs_En in the following code.
Synplicity it as a Warning.

Thanks for your comments..

Mohammed khader.

Regs:process(Clk)
begin
if(Dec_En = '1' and RISING_EDGE(Clk))then
Decode_Reg <= srl_buff;
end if;
if(Addrs_En = '1' and RISING_EDGE(Clk))then
Addrs_Reg <= std_logic_vector(Decode_Reg(12 downto 6));
end if;
if(Data_En = '1' and RISING_EDGE(Clk))then
Data_Reg <= Decode_Reg;
end if;
end process Regs;


In all conditions I see rising_edge(clk). So when there no rising_edge
nothing is changed.
So I don't see a reason adding other signals. The following description is
the same:

process(clk)
begin
if rising_edge(clk) then
if dec_en='1' then Decode_Reg <= srl_buff; end if;
if addrs_en='1' then Addrs_Reg <= std_logic_vector(Decode_Reg(12 downto
6)); end if;
if data_en='1' then Data_Reg <= Decode_Reg; end if;
end if;
end process;

Egbert Molenkamp
Click to expand...
 
Mohammed A khader wrote:
HI all,

Is it necesary to specify Dec_En and Addrs_En in the following code.
Synplicity it as a Warning.
Click to expand...
The sensitivity list is primarily for simulation -- most synthesis
tools ignore it except for giving a warning if it isn't complete.

Regs:process(Clk)
begin
if(Dec_En = '1' and RISING_EDGE(Clk))then
Decode_Reg <= srl_buff;
end if;
if(Addrs_En = '1' and RISING_EDGE(Clk))then
Addrs_Reg <= std_logic_vector(Decode_Reg(12 downto 6));
end if;
if(Data_En = '1' and RISING_EDGE(Clk))then
Data_Reg <= Decode_Reg;
end if;
end process Regs;
Click to expand...
You've had one alternative suggested already. Personally, I think I'd
skip the sensitivity list entirely, and use a wait instead:

Regs : process is
begin
wait until rising_edge(Clk);
if Dec_En = '1' then
Decode_Reg <= srl_buff;
end if;
if Addrs_En = '1' then
Addrs_Reg <= std_logic_vector(Decode_Reg(12 downto 6));
end if;
if Data_En = '1' then
Data_Reg <= Decode_Reg;
end if;
end Process;

--
Later,
Jerry.

The universe is a figment of its own imagination.
 
wait isn't only for simulation??


"Jerry Coffin" <jcoffin@taeus.com> a écrit dans le message de news:
1109800013.601618.283170@f14g2000cwb.googlegroups.com...
Mohammed A khader wrote:
HI all,

Is it necesary to specify Dec_En and Addrs_En in the following code.
Synplicity it as a Warning.

The sensitivity list is primarily for simulation -- most synthesis
tools ignore it except for giving a warning if it isn't complete.

Regs:process(Clk)
begin
if(Dec_En = '1' and RISING_EDGE(Clk))then
Decode_Reg <= srl_buff;
end if;
if(Addrs_En = '1' and RISING_EDGE(Clk))then
Addrs_Reg <= std_logic_vector(Decode_Reg(12 downto 6));
end if;
if(Data_En = '1' and RISING_EDGE(Clk))then
Data_Reg <= Decode_Reg;
end if;
end process Regs;

You've had one alternative suggested already. Personally, I think I'd
skip the sensitivity list entirely, and use a wait instead:

Regs : process is
begin
wait until rising_edge(Clk);
if Dec_En = '1' then
Decode_Reg <= srl_buff;
end if;
if Addrs_En = '1' then
Addrs_Reg <= std_logic_vector(Decode_Reg(12 downto 6));
end if;
if Data_En = '1' then
Data_Reg <= Decode_Reg;
end if;
end Process;

--
Later,
Jerry.

The universe is a figment of its own imagination.
Click to expand...
 
KCL wrote:
wait isn't only for simulation??
Click to expand...
No -- within certain limits, wait can be synthesized. First of all, it
has to be a "wait until", not a "wait for". Second, it should be the
first statement in the process. Third, the conditions you can use are
pretty restricted, but rising_edge(X) is one that's allowed, at least
by most tools. Does anybody know of a tool that can't synthesize within
these limits?

--
Later,
Jerry.

The universe is a figment of its own imagination.
 
"Mohammed A khader" <am.imak@gmail.com> wrote in message
news:1109770017.670742.36360@o13g2000cwo.googlegroups.com...
HI all,

Is it necesary to specify Dec_En and Addrs_En in the following code.
Synplicity it as a Warning.

Thanks for your comments..

Mohammed khader.

Regs:process(Clk)
begin
if(Dec_En = '1' and RISING_EDGE(Clk))then
Decode_Reg <= srl_buff;
end if;
if(Addrs_En = '1' and RISING_EDGE(Clk))then
Addrs_Reg <= std_logic_vector(Decode_Reg(12 downto 6));
end if;
if(Data_En = '1' and RISING_EDGE(Clk))then
Data_Reg <= Decode_Reg;
end if;
end process Regs;

In all conditions I see rising_edge(clk). So when there no rising_edge
Click to expand...
nothing is changed.
So I don't see a reason adding other signals. The following description is
the same:

process(clk)
begin
if rising_edge(clk) then
if dec_en='1' then Decode_Reg <= srl_buff; end if;
if addrs_en='1' then Addrs_Reg <= std_logic_vector(Decode_Reg(12 downto
6)); end if;
if data_en='1' then Data_Reg <= Decode_Reg; end if;
end if;
end process;

Egbert Molenkamp
 
By experience you shouldn't put other condition in an if(rising_edge(clk) )
otherwise your signal clk wouldn't be considerated as a clock by synthetyzer
so edgbert proposition is the good solution

"Jim Lewis" <Jim@SynthWorks.com> a écrit dans le message de news:
112c4rv63bts0fa@corp.supernews.com...
Mohammed,
What Egbert has proposed will work well in nearly
all synthesis tools.

What you coded, while simulation wise is correct
and is compliant with 1076.6-2004 (the VHDL RTL Synthesis
Specification) I would not be surprised to find that
some vendors do not fully support it yet.

To get them to fully support it, I would turn in your
code as a but and indicate to them that the code is
1076.6-2004 compliant.

Cheers,
Jim Lewis
vice-chair 1076.6 working group
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


"Mohammed A khader" <am.imak@gmail.com> wrote in message
news:1109770017.670742.36360@o13g2000cwo.googlegroups.com...

HI all,

Is it necesary to specify Dec_En and Addrs_En in the following code.
Synplicity it as a Warning.

Thanks for your comments..

Mohammed khader.

Regs:process(Clk)
begin
if(Dec_En = '1' and RISING_EDGE(Clk))then
Decode_Reg <= srl_buff;
end if;
if(Addrs_En = '1' and RISING_EDGE(Clk))then
Addrs_Reg <= std_logic_vector(Decode_Reg(12 downto 6));
end if;
if(Data_En = '1' and RISING_EDGE(Clk))then
Data_Reg <= Decode_Reg;
end if;
end process Regs;


In all conditions I see rising_edge(clk). So when there no rising_edge
nothing is changed.
So I don't see a reason adding other signals. The following description
is the same:

process(clk)
begin
if rising_edge(clk) then
if dec_en='1' then Decode_Reg <= srl_buff; end if;
if addrs_en='1' then Addrs_Reg <= std_logic_vector(Decode_Reg(12
downto 6)); end if;
if data_en='1' then Data_Reg <= Decode_Reg; end if;
end if;
end process;

Egbert Molenkamp
Click to expand...
 
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