Is it good enough to assume that

  • Thread starter parag_paul@hotmail.com
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parag_paul@hotmail.com

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the absence of procedural drivers is enough to say that it has a
continuous assign,
I have another question too

1. What is quasi conta assign
 
On Thu, 21 Feb 2008 05:15:10 -0800 (PST),
"parag_paul@hotmail.com" wrote:

the absence of procedural drivers is enough to say that it has a
continuous assign,
eh? I have no idea what you are talking about.

A variable that is declared but never written plainly has
no procedural drivers, but nor does it have a continuous
assignment to it. Your statement is therefore proven false.

The *presence* of procedural drivers on a variable in
SystemVerilog is enough to make it illegal for there
to be any continuous assignment to it.

1. What is quasi conta assign
eh? I have heard people speak of "quasi continuous
assignment" when describing Verilog's procedural
"assign" statement. Is that what you mean?
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