Is Function/Task synthesizable?

[humann]

The concept of "code reuse" in software is function.

Every software guy knows that calling a function in C is
1. push parameters in stack
2. point pc counter to the begin address of the function

what happens in Verilog if I call a function, both in simulation or in
a chip?

1. Is function/task in Verilog synthesizable? or It works just in
simulation.
2. If I call a function several times, what does it means?
2.1 I use a hardware several time
2.2 I duplicate hardware in Chip.
3. How can I use a hardware in a "time-sharing" fashion? (for
Example: to save power or save area)

 

[Ryan]

On Jan 3, 3:54 am, humann <hongqing...@gmail.com> wrote:

The concept of "code reuse" in software is function.

Every software guy knows that calling a function in C is
1. push parameters in stack
2. point pc counter to the begin address of the function

what happens in Verilog if I call a function, both in simulation or in
a chip?

1. Is function/task in Verilog synthesizable? or It works just in
simulation.
2. If I call a function several times, what does it means?
2.1 I use a hardware several time
2.2 I duplicate hardware in Chip.
3. How can I use a hardware in a "time-sharing" fashion? (for
Example: to save power or save area)

Whether it is synthesizable or not, largely depends on how you use
it. Since you obviously know software I assume you have books on the
subject. Since you are trying to learn about hardware synthesis, I
recommend the same for this subject. A classic is HDL CHIP DESIGN by
Doublas J. Smith.

When software types first dive into synthesis they often find they
have a hard time meeting timing. That is because they are only
thinking logically and not physically. Ultimately you are doing
circuit design, and you need to know what circuit will be generated by
the code you write. I like this book because it approaches HDL from a
circuit design perspective instead of a language perspective. It give
examples of most of the basic building block circuits you would want
to use, and examples in both verilog and vhdl that will generate said
circuit.

 

[Kevin Neilson]

humann wrote:

The concept of "code reuse" in software is function.

Every software guy knows that calling a function in C is
1. push parameters in stack
2. point pc counter to the begin address of the function

what happens in Verilog if I call a function, both in simulation or in
a chip?

1. Is function/task in Verilog synthesizable? or It works just in
simulation.
2. If I call a function several times, what does it means?
2.1 I use a hardware several time
2.2 I duplicate hardware in Chip.
3. How can I use a hardware in a "time-sharing" fashion? (for
Example: to save power or save area)

Historically, code reuse in HDL has used the "module", not the function.
Instantiating a module multiple times is akin to calling a function
multiple times. However, synthesizers are getting pretty good at
synthesizing Verilog functions now, which sometimes allows for a nicer
means of abstraction. The analog to software functions, is, however,
not direct. A function call occurs in zero time and multiple function
calls occur across die space, not time. (The same is usually true of
synthesizing 'for' loops: the index is spread across die space, not
time.) That is, calling a function twice will not use the same
hardware. (A lot of the function calls I use are 'constant' functions,
like log2, and get resolved presynthesis, using no hardware.)

Timeslicing is a time-honored technique. An optimal design will usually
use the least amount of gates, timesliced so they run at the fastest
possible speed. Timeslicing usually must be coded explicitly and can't
be done by calling functions at different times.
-Kevin

 

[humann]

On Jan 3, 4:25 pm, Ryan <Ryan.Warner...@gmail.com> wrote:

On Jan 3, 3:54 am, humann <hongqing...@gmail.com> wrote:



The concept of "code reuse" in software is function.

Every software guy knows that calling a function in C is
1. push parameters in stack
2. point pc counter to the begin address of the function

what happens in Verilog if I call a function, both in simulation or in
a chip?

1. Is function/task in Verilog synthesizable? or It works just in
simulation.
2. If I call a function several times, what does it means?
2.1 I use a hardware several time
2.2 I duplicate hardware in Chip.
3. How can I use a hardware in a "time-sharing" fashion? (for
Example: to save power or save area)

Whether it is synthesizable or not, largely depends on how you use
it. Since you obviously know software I assume you have books on the
subject. Since you are trying to learn about hardware synthesis, I
recommend the same for this subject. A classic is HDL CHIP DESIGN by
Doublas J. Smith.

When software types first dive into synthesis they often find they
have a hard time meeting timing.
What does "meeting timing" means? timing analyse?

That is because they are only thinking logically and not physically
This description is to the point. It is the most difficult part for

me
to learn verilog.

Ultimately you are doing
circuit design, and you need to know what circuit will be generated by
the code you write.
I will try to "thinking more physically".

There are any tools which I can see my code as circuits intuitively?
Synopsys Design Compiler? There are any good tutorials for it with
example code?

I like this book because it approaches HDL from a
circuit design perspective instead of a language perspective. It give
examples of most of the basic building block circuits you would want
to use, and examples in both verilog and vhdl that will generate said
circuit.
Thank you for your tip.

 

[humann]

On Jan 3, 7:39 pm, Kevin Neilson <kevin_neil...@removethiscomcast.net>
wrote:

humann wrote:
The concept of "code reuse" in software is function.

Every software guy knows that calling a function in C is
1. push parameters in stack
2. point pc counter to the begin address of the function

what happens in Verilog if I call a function, both in simulation or in
a chip?

1. Is function/task in Verilog synthesizable? or It works just in
simulation.
2. If I call a function several times, what does it means?
2.1 I use a hardware several time
2.2 I duplicate hardware in Chip.
3. How can I use a hardware in a "time-sharing" fashion? (for
Example: to save power or save area)

Historically, code reuse in HDL has used the "module", not the function.
Instantiating a module multiple times is akin to calling a function
multiple times. However, synthesizers are getting pretty good at
synthesizing Verilog functions now, which sometimes allows for a nicer
means of abstraction. The analog to software functions, is, however,
not direct. A function call occurs in zero time and multiple function
calls occur across die space, not time.
Does "a function call occurs in zero time" mean "initial" in verilog?

I can
hardly image it in hardware.
It seems to me as a reset button or a piece of circuits, which is
active just during power-up.

(The same is usually true of
synthesizing 'for' loops: the index is spread across die space, not
time.) That is, calling a function twice will not use the same
hardware. (A lot of the function calls I use are 'constant' functions,
like log2, and get resolved presynthesis, using no hardware.)
what does "resoved presynthesis, using no hardware"? Do you means the

synthsizer calculates log2
(0.30103) and code it in binary float number(0.01001)?

timeslicing is a time-honored technique. An optimal design will usually
use the least amount of gates, timesliced so they run at the fastest
possible speed. Timeslicing usually must be coded explicitly and can't
be done by calling functions at different times.
There are any code example to show how to do it ?
-Kevin

Thank you for your insidely explanation. I got my most questions
answered.

 

[Petter Gustad]

humann <hongqing.hu@gmail.com> writes:

1. Is function/task in Verilog synthesizable? or It works just in
simulation.

A function can be just a block of combinatorial logic and hence
synthesizable. A task is the same but with more than one output.

2. If I call a function several times, what does it means?
2.1 I use a hardware several time
2.2 I duplicate hardware in Chip.

Mostly two (or more) instances of the same combinatorial block.

3. How can I use a hardware in a "time-sharing" fashion? (for
Example: to save power or save area)

You can use resource sharing to share a piece of logic but it's very
dependant upon the synthesis tool how it is handled.

Petter

--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

 

[Kevin Neilson]

humann wrote:

On Jan 3, 7:39 pm, Kevin Neilson <kevin_neil...@removethiscomcast.net
wrote:
humann wrote:
The concept of "code reuse" in software is function.
Every software guy knows that calling a function in C is
1. push parameters in stack
2. point pc counter to the begin address of the function
what happens in Verilog if I call a function, both in simulation or in
a chip?
1. Is function/task in Verilog synthesizable? or It works just in
simulation.
2. If I call a function several times, what does it means?
2.1 I use a hardware several time
2.2 I duplicate hardware in Chip.
3. How can I use a hardware in a "time-sharing" fashion? (for
Example: to save power or save area)
Historically, code reuse in HDL has used the "module", not the function.
Instantiating a module multiple times is akin to calling a function
multiple times. However, synthesizers are getting pretty good at
synthesizing Verilog functions now, which sometimes allows for a nicer
means of abstraction. The analog to software functions, is, however,
not direct. A function call occurs in zero time and multiple function
calls occur across die space, not time.
Does "a function call occurs in zero time" mean "initial" in verilog?
I can
hardly image it in hardware.
It seems to me as a reset button or a piece of circuits, which is
active just during power-up.

In hardware, the function obviously takes finite time, but can only be

combinatorial. The result of the function call must be registered in
some clocked process.

(The same is usually true of
synthesizing 'for' loops: the index is spread across die space, not
time.) That is, calling a function twice will not use the same
hardware. (A lot of the function calls I use are 'constant' functions,
like log2, and get resolved presynthesis, using no hardware.)
what does "resoved presynthesis, using no hardware"? Do you means the
synthsizer calculates log2
(0.30103) and code it in binary float number(0.01001)?

An example is that I often use log2 to calculate a bus width. For example,

wire [log2(32)-1:0] databus;

The log2(32) is calculated before synthesis and the bus is made to be
five bits wide. The function call doesn't get "called" real-time, i.e.,
doesn't resolve into logic that changes on clock edges.

timeslicing is a time-honored technique. An optimal design will usually
use the least amount of gates, timesliced so they run at the fastest
possible speed. Timeslicing usually must be coded explicitly and can't
be done by calling functions at different times.
There are any code example to show how to do it ?

This might not be the best example, but the chapter in this manual on
"Semi-Parallel FIR Filters" shows how to increase/decrease hardware
usage based on desired data rate:
http://www.xilinx.com/bvdocs/userguides/ug073.pdf

I don't believe there is any code; it's just schematics. But as Ryan
says, it's really more important to visualize the circuit than the code
itself. If you can't visualize the hardware you are describing, you
will have trouble writing code for it.

-Kevin


Thank you for your insidely explanation. I got my most questions
answered.

 

[mk]

On Fri, 04 Jan 2008 22:25:04 +0100, Petter Gustad
<newsmailcomp6@gustad.com> wrote:

humann <hongqing.hu@gmail.com> writes:

1. Is function/task in Verilog synthesizable? or It works just in
simulation.

A function can be just a block of combinatorial logic and hence
synthesizable. A task is the same but with more than one output.

Tasks are slightly different in that they can have sequential elements

too.

2. If I call a function several times, what does it means?
2.1 I use a hardware several time
2.2 I duplicate hardware in Chip.

Mostly two (or more) instances of the same combinatorial block.

3. How can I use a hardware in a "time-sharing" fashion? (for
Example: to save power or save area)

You can use resource sharing to share a piece of logic but it's very
dependant upon the synthesis tool how it is handled.

Or one can implement explicity resource sharing by controlling the
inputs and outputs of the hardware. Say you have a design which needs
to implement an algorithm needing several multiplications. Instead of
using a separate multiplier (ie making a function call) for each
multiplication, one can instantiate one multiplier and change its
inputs over several cycles to different values and store the outputs
to different locations. This requires implementation of a state
machine which controls which values are muxed at the inputs and which
the results go each cycle but it can be a huge area/power saver IF one
can afford the latency it generates. There are always solutions in the
middle, ie. instead of using one multiplier and getting a latency of N
(assuming there were N multipliers in the original requirement) one
can use 2 multipliers and reduce the latency to N/2 etc.

 

[Dwayne Dilbeck]

The standard does not allow any timing control in a function. That means no
waiting for an event to happen before completion or delaying the results.

Given that most functions can be synthesized, as long as thier inputs are
sythesizable and the internal function uses synthesizable constructs. IE.
No PLI code, and system tasks.

Tasks are allowed to contain timing elements. That makes task much more
difficult to synthesize. If you wrote a task exactly like a function in
that it had no timing elements. The odds are good it could be synthesized.

When you start adding timing controls to the task, like @(posedge enable1)
to the task things get more complicated. Some times the task can be
synthesized sometimes not. It really depends on the coding. style and
constructs used.

Unfortunately I am not aware of an IEEE subset of verilog that is declared
synthesizable. VHDL does 1076.6. I believe there was a IEEE 1364.1 subset
that was being worked on a long time ago, but I don't know what happened to
it.

To make matters worse some synthesizers have started synthesizing system
task such as $display, $stop, and $finish. Granted these are used primarily
by synthesizable testbenches in emulation and acceleration. Not actual
chips.

"humann" <hongqing.hu@gmail.com> wrote in message
news:bd3497ba-b19b-4145-9761-4b619128e207@i3g2000hsf.googlegroups.com...

The concept of "code reuse" in software is function.

Every software guy knows that calling a function in C is
1. push parameters in stack
2. point pc counter to the begin address of the function

what happens in Verilog if I call a function, both in simulation or in
a chip?

1. Is function/task in Verilog synthesizable? or It works just in
simulation.
2. If I call a function several times, what does it means?
2.1 I use a hardware several time
2.2 I duplicate hardware in Chip.
3. How can I use a hardware in a "time-sharing" fashion? (for
Example: to save power or save area)

 

[mk]

On Mon, 7 Jan 2008 17:09:51 -0800, "Dwayne Dilbeck"
<ddilbeck@yahoo.com> wrote:

Unfortunately I am not aware of an IEEE subset of verilog that is declared
synthesizable. VHDL does 1076.6. I believe there was a IEEE 1364.1 subset
that was being worked on a long time ago, but I don't know what happened to
it.

http://ieeexplore.ieee.org/servlet/opac?punumber=4140790

 

[Dwayne Dilbeck]

Thanks!!

My company just changed thier IEEE contract. Sucks! If I had this link 9
days ago I would be able to download it and read it now. Now I guess I
will have to buy it and get my company to re-imberse me.

"mk" <kal*@dspia.*comdelete> wrote in message
news:5f46o3d54asrcn6hkacdrvqmgdghdjfgda@4ax.com...

On Mon, 7 Jan 2008 17:09:51 -0800, "Dwayne Dilbeck"
ddilbeck@yahoo.com> wrote:

Unfortunately I am not aware of an IEEE subset of verilog that is declared
synthesizable. VHDL does 1076.6. I believe there was a IEEE 1364.1
subset
that was being worked on a long time ago, but I don't know what happened
to
it.

http://ieeexplore.ieee.org/servlet/opac?punumber=4140790