Is FPGA fully static?

[Raivo Nael]

If i wish for debuging purposes lower clock frequency that i supply
for FPGA from external source can i always do it?

For example if i have borad that is intended to run with 40MHz
external clock source and for debuging purposes i will supply 40 Hz
clock, does circuit behave exactly as on higher speed expect that all
happens 1 000 000 x slower or is this situation more complicated?

regards,
Raivo

 

[B. Joshua Rosen]

On Thu, 29 Jan 2004 05:46:05 -0800, Raivo Nael wrote:

If i wish for debuging purposes lower clock frequency that i supply
for FPGA from external source can i always do it?

For example if i have borad that is intended to run with 40MHz
external clock source and for debuging purposes i will supply 40 Hz
clock, does circuit behave exactly as on higher speed expect that all
happens 1 000 000 x slower or is this situation more complicated?

regards,
Raivo

The DCMs in Xilinx parts have a minimum frequency requirement, it's in the
neighborhood of 25MHz. If you want to use a slow clock you can't use the
DCMs, you will have to use the input clock directly.

 

[Peter Alfke]

If you do NOT use the DCM, you can go as low as you want.
The DCM has a min input frequency of 25 MHz,( except for the FS mode
where the min output frequency is 25 MHz, and the input frequency can
then be significantly lower).

Peter Alfke, Xilinx
---------------------------
Raivo Nael wrote:

If i wish for debuging purposes lower clock frequency that i supply
for FPGA from external source can i always do it?

For example if i have borad that is intended to run with 40MHz
external clock source and for debuging purposes i will supply 40 Hz
clock, does circuit behave exactly as on higher speed expect that all
happens 1 000 000 x slower or is this situation more complicated?

regards,
Raivo

 

[Jon Elson]

Raivo Nael wrote:

If i wish for debuging purposes lower clock frequency that i supply
for FPGA from external source can i always do it?

For example if i have borad that is intended to run with 40MHz
external clock source and for debuging purposes i will supply 40 Hz
clock, does circuit behave exactly as on higher speed expect that all
happens 1 000 000 x slower or is this situation more complicated?


The older Xilinx FPGAs that didn't have clock multipliers and DLLs

are totally static. You could clock them with a debounced pushbutton
if you wanted to. I think even the current ones can be used like this, but
you have to avoid the PLL and DLL components, as they do have a
specified min and max frequency.

I have several products that run Xilinx FPGAs WAY below their maximum
clock frequency, because that is all the speed needed in the application.
I have a device I'm debugging right now using an older 5V Spartan chip
that has no continuous clock whatsoever. There are a few clocks that
are really strobes from other devices, but the part is largely
combinatorial.
It routes signals around unpopulated bus slots in a piece of gear, reports
which slots have what boards in them, if any, and such things.

Jon

 

[Ray Andraka]

There is a caveat on the older devices: The 4000 series had a limitation on
the amount of time the clock could be held high to CLB RAM due to power
dissipation concerns. I can't remember now if that included the 4000E series
or not, I don't think it did but am not sure. So while those particular
devices were static, you had to be careful not to park the clock high if you
had any CLBRAMs in your design.

Other than that, and the DLL/DCM restrictions others have mentioned, there is
no minimum clock.


--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Ken]

If you do NOT use the DCM, you can go as low as you want.
The DCM has a min input frequency of 25 MHz,( except for the FS mode
where the min output frequency is 25 MHz, and the input frequency can
then be significantly lower).

FS mode?

Ken

 

[Peter Alfke]

Acronyms....
FS stands for Frequency Synthesis, where the input frequency can be
simultaneously multiplied and divided by a range of number choices (
presently 1...32)
The other modes are
Clock De-skew and
Phase Shifting.
All this is explained in excruciating detail in the Virtex-II and
Virtex-IIPro documentation.

Peter Alfke, Xilinx Applications
=========
Ken wrote:

If you do NOT use the DCM, you can go as low as you want.
The DCM has a min input frequency of 25 MHz,( except for the FS mode
where the min output frequency is 25 MHz, and the input frequency can
then be significantly lower).

FS mode?

Ken