Is a logic synthesizer smart enough?

N

Neeraj

Guest
Hi everyone,
First, a little context. A friend of mine wanted to design a
synthesizable circuit which would count the number of consecutive zeros
in a byte in ONE clock cycle (the byte in question being known
beforehand). His solution used a for loop in the following manner:

//----code----
integer i;
integer count_zeros; //keeps track of the number of zeros
reg array [7:0]; //the byte in question is stored here
//clock defined
//count_zeros initialized to zero at start of simulation
//----code----
always @ (posedge clock) begin
for(i = 0; i < 8; i=i + 1) begin
if(array == 0) begin
count_zeros = count_zeros + 1;
end
end
end

Now, the question he asked me was: If the for loop gets synthesized to
a counter, what clock does it work on? In other words, what signal does
the counter use as a reference to increment its value?
My answer was that the logic synthesizer would be smart enough to
create a signal that basically would be 8 times the clock frequency
(since it needed to increment eight times in one clock).
What I'm wondering is, is my answer correct? Would the logic
synthesizer actually be astute enough to generate the required clock?
Thanks for any help/ comments,
Ciao.
 
Guys thanks for your answers! I think the fog's lifting around my head!
:)

Glen wrote:
The name of this circuit is a priority encoder, given a binary
number it will find the first '1' bit. The loop will be
expanded as combinatorial logic, proportional to the maximum
number of iterations. About half the logic goes away in the
synthesizer as redundant, though.
Click to expand...
Tom said:
Your answer is not correct. How could the synthesizer magically create
a clock that's 8 times faster than the original clock?
The synthesizer will unroll the loop and basically create 8
conditional
incrementors and then start optimiziming away whatever it can.
Click to expand...
Could you enlighten me as to how the synthesizer would optimize the
code? Would it discard some of the incrementors?
Does anyone out there have any pointers to webpages or books devoted to
how synthesizers actually work?
Thanks for the assist! :)
 
Guys thanks for your answers! I think the fog's lifting around my head!
:)

Glen wrote:
The name of this circuit is a priority encoder, given a binary
number it will find the first '1' bit. The loop will be
expanded as combinatorial logic, proportional to the maximum
number of iterations. About half the logic goes away in the
synthesizer as redundant, though.
Click to expand...
Tom said:
Your answer is not correct. How could the synthesizer magically create
a clock that's 8 times faster than the original clock?
The synthesizer will unroll the loop and basically create 8
conditional
incrementors and then start optimiziming away whatever it can.
Click to expand...
Could you enlighten me as to how the synthesizer would optimize the
code? Would it discard some of the incrementors?
Does anyone out there have any pointers to webpages or books devoted to
how synthesizers actually work?
Thanks for the assist! :)
 
I would have used this to replace your codes.
But what does that *consecutive* mean? Your code doesn't do that.
// ------------------------------------
reg [7:0] array;
reg [2:0] sum;
reg [2:0] count_zeros;

always @ (posedge clk ...)
begin
if (...)

else
count_zeros <= (((~array[0]) +
(~array[1])) +
((~array[2]) +
(~array[3])) )+
( ((~array[4]) +
(~array[5])) +
( (~array[6]) +
(~array[7])) );
end
// ------------------------------------ End



"Neeraj" <neeraj.venkat@wipro.com> wrote in message
news:1099911788.124145.107900@f14g2000cwb.googlegroups.com...
Hi everyone,
First, a little context. A friend of mine wanted to design a
synthesizable circuit which would count the number of consecutive zeros
in a byte in ONE clock cycle (the byte in question being known
beforehand). His solution used a for loop in the following manner:

//----code----
integer i;
integer count_zeros; //keeps track of the number of zeros
reg array [7:0]; //the byte in question is stored here
//clock defined
//count_zeros initialized to zero at start of simulation
//----code----
always @ (posedge clock) begin
for(i = 0; i < 8; i=i + 1) begin
if(array == 0) begin
count_zeros = count_zeros + 1;
end
end
end

Now, the question he asked me was: If the for loop gets synthesized to
a counter, what clock does it work on? In other words, what signal does
the counter use as a reference to increment its value?
My answer was that the logic synthesizer would be smart enough to
create a signal that basically would be 8 times the clock frequency
(since it needed to increment eight times in one clock).
What I'm wondering is, is my answer correct? Would the logic
synthesizer actually be astute enough to generate the required clock?
Thanks for any help/ comments,
Ciao.
Click to expand...
 
Reverend wrote:
I would have used this to replace your codes.
Click to expand...
Why? It is not shorter, it is not more self expalinable and it is not
better maintainable (all IMHO of course).

But what does that *consecutive* mean? Your code doesn't do that.
Click to expand...
I suppose it means 'adjadent'. Then a loop must be used, resetting the
count if a one is detected (and determine if the current count is higher
than the previous count).

Paul.


// ------------------------------------
reg [7:0] array;
reg [2:0] sum;
reg [2:0] count_zeros;

always @ (posedge clk ...)
begin
if (...)

else
count_zeros <= (((~array[0]) +
(~array[1])) +
((~array[2]) +
(~array[3])) )+
( ((~array[4]) +
(~array[5])) +
( (~array[6]) +
(~array[7])) );
end
// ------------------------------------ End
Click to expand...
 
Reverend wrote:

I would have used this to replace your codes.
But what does that *consecutive* mean? Your code doesn't do that.
// ------------------------------------
reg [7:0] array;
reg [2:0] sum;
reg [2:0] count_zeros;

always @ (posedge clk ...)
begin
if (...)

else
count_zeros <= (((~array[0]) +
(~array[1])) +
((~array[2]) +
(~array[3])) )+
( ((~array[4]) +
(~array[5])) +
( (~array[6]) +
(~array[7])) );
end
// ------------------------------------ End
Click to expand...
I don't see why that is better than the original.
The original code (loop) code like the one above does count ALL
zeros not consecutive zeros ...
To count consecutive zeros, a simple decoder might be a better choice:

casex(array)
begin
8'b1???_????: count = 3'h0;
8'b1???_????: count = 3'h0;
8'b1???_????: count = 3'h0;
8'b1???_????: count = 3'h0;
8'b1???_????: count = 3'h0;
end

"Neeraj" <neeraj.venkat@wipro.com> wrote in message
news:1099911788.124145.107900@f14g2000cwb.googlegroups.com...
Hi everyone,
First, a little context. A friend of mine wanted to design a
synthesizable circuit which would count the number of consecutive zeros
in a byte in ONE clock cycle (the byte in question being known
beforehand). His solution used a for loop in the following manner:

//----code----
integer i;
integer count_zeros; //keeps track of the number of zeros
reg array [7:0]; //the byte in question is stored here
//clock defined
//count_zeros initialized to zero at start of simulation
//----code----
always @ (posedge clock) begin
for(i = 0; i < 8; i=i + 1) begin
if(array == 0) begin
count_zeros = count_zeros + 1;
end
end
end

Now, the question he asked me was: If the for loop gets synthesized to
a counter, what clock does it work on? In other words, what signal does
the counter use as a reference to increment its value?
My answer was that the logic synthesizer would be smart enough to
create a signal that basically would be 8 times the clock frequency
(since it needed to increment eight times in one clock).
What I'm wondering is, is my answer correct? Would the logic
synthesizer actually be astute enough to generate the required clock?
Thanks for any help/ comments,
Ciao.
Click to expand...
 
Reverend wrote:

I would have used this to replace your codes.
But what does that *consecutive* mean? Your code doesn't do that.
// ------------------------------------
reg [7:0] array;
reg [2:0] sum;
reg [2:0] count_zeros;

always @ (posedge clk ...)
begin
if (...)

else
count_zeros <= (((~array[0]) +
(~array[1])) +
((~array[2]) +
(~array[3])) )+
( ((~array[4]) +
(~array[5])) +
( (~array[6]) +
(~array[7])) );
end
// ------------------------------------ End
Click to expand...

Sorry pressed "send" before I finished typing ....

I don't see why that is better than the original.
The original code (loop) code like the one above does count ALL
zeros not consecutive zeros ...
To count consecutive zeros, a simple decoder might be a better choice:

case(array)
begin
8'b1???_????: count = 4'h0;
8'b01??_????: count = 4'h1;
8'b001?_????: count = 4'h2;
8'b0001_????: count = 4'h3;
8'b0000_1???: count = 4'h4;
8'b0000_01??: count = 4'h5;
8'b0000_001?: count = 4'h6;
8'b0000_0001: count = 4'h7;
8'b0000_0000: count = 4'h8;
end

Now this will count consecutive zeros from right to left.
It should be obvious how to reverse this. Also note that
"count" must be 4 bits wide, so you can count 0..8 zeros.

Regards,
rudi
=============================================================
Rudolf Usselmann, ASICS World Services, http://www.asics.ws
Your Partner for IP Cores, Design, Verification and Synthesis
 
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