IP core implementation of multiplier on FPGA Spartan 3e

[deepak]

i was tryin to implement an ip core of multiplier on fpga spartan 3e,but in the synthesysing process it is showing some error about routing problems.

 

[Jon]

Can you describe the multiplier? (Width, anything special about it, does it use the multiplication operator)

Is it using the embedded h/w multipliers in the s3e? What's the exact error message?

Jon

 

[deepak]

On Wednesday, January 16, 2013 7:43:41 AM UTC-8, Jon wrote:

Can you describe the multiplier? (Width, anything special about it, does it use the multiplication operator)



Is it using the embedded h/w multipliers in the s3e? What's the exact error message?



Jon

I used the ip core of multiplier which is available in xilinx 12.2,then in the next step i assigned pins in the plan ahead.after that when i synthesised it gave these warnings:
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <a> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <b> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1306 - Output <p> is never assigned.
,
Basically i wanted to learn how to implement an ip core on fpga kit,
i will be very thankful for any kind of help!
thanks.

 

[deepak]

On Thursday, January 17, 2013 4:32:18 AM UTC-8, deepak wrote:

On Wednesday, January 16, 2013 7:43:41 AM UTC-8, Jon wrote:

Can you describe the multiplier? (Width, anything special about it, does it use the multiplication operator)







Is it using the embedded h/w multipliers in the s3e? What's the exact error message?







Jon



I used the ip core of multiplier which is available in xilinx 12.2,then in the next step i assigned pins in the plan ahead.after that when i synthesised it gave these warnings:

WARNING:Xst:647 - Input &lt;clk&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <a> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <b> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:1306 - Output <p> is never assigned.

,

Basically i wanted to learn how to implement an ip core on fpga kit,

i will be very thankful for any kind of help!

thanks.

i was using a 2bit input