IO pin question

F

fasf

Guest
Hi,
i'm new with FPGA,so excuse me for my question...
Any FPGA is composed by banks, each with its Vdd: IO pins of that bank
can be used with each logic with high state and low state between 0-
vdd?
For example, if Vdd is 3V, i can use IO pins for LVDS signals (1.8V
+-200mV)?And for TTL signal 0-5V?
Thanks
 
Hi,
i'm new with FPGA,so excuse me for my question...
Any FPGA is composed by banks, each with its Vdd: IO pins of that bank
can be used with each logic with high state and low state between 0-
vdd?
For example, if Vdd is 3V, i can use IO pins for LVDS signals (1.8V
+-200mV)?And for TTL signal 0-5V?
Thanks
Click to expand...
The user guide will tell you what bank voltage you need for the IO standar
you are going to use. I'm not really sure what you are trying to sa
regarding the LVDS standard. You cant just connect any old voltage onto th
bank.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
 
Thanks for your answer, but i have a question...
from user guide i saw that LVDS_2.5 requires Vcc=2.5V....i can
implement LVDS_2.5 with Vcc=3.3V?
Click to expand...
No, if it says 2.5V then that is the voltage on the bank you need.
believe that some FPGAs like Spartan 6 have a 3.3V LVDS.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
 
Thanks for your answer, but i have a question...
from user guide i saw that LVDS_2.5 requires Vcc=2.5V....i can
implement LVDS_2.5 with Vcc=3.3V?
 
On 18 Okt., 17:04, fasf <silusilus...@gmail.com> wrote:
i'm new with FPGA,so excuse me for my question...
Any FPGA is composed by banks, each with its Vdd: IO pins of that bank
Click to expand...
Wrong. Some FPGAs have several banks, maybe most, but not every.

Please do yourself a favor and start giving detailed information about
the device. E.g. write wthat the databook says about this topics. That
would really help us giving answers. There is no asnwer to your
question that is valid for all Fpgas

bye Thomas
 
On 19 Ott, 13:23, Thomas Stanka <usenet_nospam_va...@stanka-web.de>
wrote:
Please do yourself a favor and start giving detailed information about
the device.....
Click to expand...
You're right...I have a Spartan6 and i want to use its LVDS input...i
want to connect LVDS traces to differential I/O pins located in a bank
powered by 3.3V. In an earlier version of the board, the same traces
are connected to differential I/O pins located in a bank powered by
2.5V. connect LVDS to a bank powered by 3.3V could be a problem?
 
Please go and read the Spartan 6 DC data sheet and the Select IO guide an
I am sure that all your questions will be answered. You are askin
questions that you could find out quite easily by yourself. I am not sayin
I dont want to give you the answer, but in the long term I think it woul
be better that you did it.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
 
On 10/20/2010 2:37 PM, fasf wrote:
On 20 Ott, 09:46, "maxascent"
maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:
Please go and read the Spartan 6 DC data sheet and the Select IO guide and
I am sure that all your questions will be answered. You are asking
questions that you could find out quite easily by yourself. I am not saying
I dont want to give you the answer, but in the long term I think it would
be better that you did it.

it's what i've done and from datasheet i think it's possible, but i
asked in this newsgroup to became totally sure...in datasheet (pag 28
in SelectIO resources) i've found "LVDS_33 is used to drive TIA/EIA644
LVDS levels in a bank powered with 3.3V VCCO. Electrically the same as
LVDS_25."
So i think is possible, right?
Click to expand...
Although you quote here the datasheet which says you can transmit LVDS
from a 3.3V bank, you originally asked whether you can receive LVDS
signals in a 3.3V bank. What does the datasheet say about that? What
about termination?

Cheers, Syms.
 
On 20 Ott, 09:46, "maxascent"
<maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:
Please go and read the Spartan 6 DC data sheet and the Select IO guide and
I am sure that all your questions will be answered. You are asking
questions that you could find out quite easily by yourself. I am not saying
I dont want to give you the answer, but in the long term I think it would
be better that you did it.
Click to expand...
it's what i've done and from datasheet i think it's possible, but i
asked in this newsgroup to became totally sure...in datasheet (pag 28
in SelectIO resources) i've found "LVDS_33 is used to drive TIA/EIA644
LVDS levels in a bank powered with 3.3V VCCO. Electrically the same as
LVDS_25."
So i think is possible, right?
 
On 20 Ott, 16:26, Symon <symon_bre...@hotmail.com> wrote:
On 10/20/2010 2:37 PM, fasf wrote:

On 20 Ott, 09:46, "maxascent"
maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk>  wrote:
Please go and read the Spartan 6 DC data sheet and the Select IO guide and
I am sure that all your questions will be answered. You are asking
questions that you could find out quite easily by yourself. I am not saying
I dont want to give you the answer, but in the long term I think it would
be better that you did it.

it's what i've done and from datasheet i think it's possible, but i
asked in this newsgroup to became totally sure...in datasheet  (pag 28
in SelectIO resources) i've found "LVDS_33 is used to drive TIA/EIA644
LVDS levels in a bank powered with 3.3V VCCO. Electrically the same as
LVDS_25."
So i think is possible, right?

Although you quote here the datasheet which says you can transmit LVDS
from a 3.3V bank, you originally asked whether you can receive LVDS
signals in a 3.3V bank.
Click to expand...
I'm interested in LVDS input

What does the datasheet say about that? What
about termination?
Click to expand...
"LVDS inputs require a parallel termination resistor,
either through the use of a discrete resistor on the PCB, or the use
of the DIFF_TERM
attribute to enable internal termination. LVDS inputs can be placed on
any I/O bank, while
LVDS outputs are only available on I/O banks 0 and 2."

So, i can use DIFF_TERM to set internal termination and, due to fact
that LVDS_3.3 is elettrically the same as LVDS_2.5, i can use 3.3V
bank to receive LVDS_2.5
Right?
 
On 18 Oct, 16:04, fasf <silusilus...@gmail.com> wrote:
Hi,
i'm new with FPGA,so excuse me for my question...
Any FPGA is composed by banks, each with its Vdd: IO pins of that bank
can be used with each logic with high state and low state between 0-
vdd?
For example, if Vdd is 3V, i can use IO pins for LVDS signals (1.8V
+-200mV)?And for TTL signal 0-5V?
Thanks
Click to expand...
You are asking a question that the tools will answer in ten minutes.
Create a design with one input driving one output. Set the input IO
standard to LVDS_whatever, set the output IO standard to CMOS_33. Put
them both in the same IO bank and compile.

Unless you are using a ten year old FPGA you can't run 5v IO.

Colin
 
On 21 Ott, 11:00, colin <colin_toog...@yahoo.com> wrote:
On 18 Oct, 16:04, fasf <silusilus...@gmail.com> wrote:

Hi,
i'm new with FPGA,so excuse me for my question...
Any FPGA is composed by banks, each with its Vdd: IO pins of that bank
can be used with each logic with high state and low state between 0-
vdd?
For example, if Vdd is 3V, i can use IO pins for LVDS signals (1.8V
+-200mV)?And for TTL signal 0-5V?
Thanks

You are asking a question that the tools will answer in ten minutes.
Create a design with one input driving one output. Set the input IO
standard to LVDS_whatever, set the output IO standard to CMOS_33. Put
them both in the same IO bank and compile.
Click to expand...
Ok, but i've never used IDE before, so i'm studying from user guide
 
On Oct 21, 7:17 am, fasf <silusilus...@gmail.com> wrote:
On 21 Ott, 11:00, colin <colin_toog...@yahoo.com> wrote:

On 18 Oct, 16:04, fasf <silusilus...@gmail.com> wrote:

Hi,
i'm new with FPGA,so excuse me for my question...
Any FPGA is composed by banks, each with its Vdd: IO pins of that bank
can be used with each logic with high state and low state between 0-
vdd?
For example, if Vdd is 3V, i can use IO pins for LVDS signals (1.8V
+-200mV)?And for TTL signal 0-5V?
Thanks

You are asking a question that the tools will answer in ten minutes.
Create a design with one input driving one output. Set the input IO
standard to LVDS_whatever, set the output IO standard to CMOS_33. Put
them both in the same IO bank and compile.

Ok, but i've never used IDE before, so i'm studying from user guide
Click to expand...
While the user guides have a lot of useful information, you'll never
get everything
you need to know without running the tools. Get used to it. This is
the way
FPGA Engineering works. There are even cases where you find an issue
that
is not described in the documentation, and Xilinx responds with "run
the tools".
Want to know which I/O bank is in which column in a Virtex 5? Can you
really use LVDS_25 in a Virtex 5 on any bank regardless of Vcco?
These
are not well explained in the documentation. For example for Virtex
5, LVDS_25
is powered by the VccAux supply, so you don't need a particular Vcco,
BUT
if you want to use DIFF_TERM, Vcco MUST be 2.5V. I don't think that
the Spartan 6 has the same issue, but there are other things you will
certainly miss if you just lay out a board and expect everything to
work
without running it through the tools. I had a very expensive flex-
laminate
that could only use 55 out of 64 bits of a DDR SO-DIMM because of
a poorly documented IOB clock routing issue in Virtex 2.

So get out the tools, run through a tutorial or two, and then use the
manuals as a reference guide.

Regards,
Gabor
 
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