Inversion of signals on synthesis

[ALuPin]

Dear Sir or Madam,

I have some phenomenon I do not know when synthesizing my VHDL
description for my
SRAM controller:

The .vho-file from Quartus is used for a timing simulation. When I
have a look at internal signals
of my controller like 'l_oe_bar', 'l_cs_bar','l_we_bar'
I see in timing simulation with Modelsim that they are right inverted
to my description, for example are
they resetted to '0' and not to my declared '1' in the VHDL
description.

The outputs of my controller are concurrently assigned like that:

OE_bar <= l_oe_bar;
CS_bar <= l_cs_bar;
WE_bar <= l_we_bar;

And yet they are inverted to the local signals.

I do not know why there seems to be a double inversion. What does
QuartusII do?

I would appreciate your help.

Kind regards

 

[glen herrmannsfeldt]

ALuPin wrote:

I have some phenomenon I do not know when synthesizing my VHDL
description for my
SRAM controller:

The .vho-file from Quartus is used for a timing simulation. When I
have a look at internal signals
of my controller like 'l_oe_bar', 'l_cs_bar','l_we_bar'
I see in timing simulation with Modelsim that they are right inverted
to my description,

Without actually looking at your files, assuming you are
working with FPGA's it is very common that inverters disappear.

Active high or low makes no difference to a lookup table,
the synthesis should generate equivalent logic, though the
actual sign may change.

-- glen

 

[Jeroen]

I have had this too with a project. When you do a functional simulation,
everything is as you want it.

I thought this is a feature called "NOT gate push back", and can be turned
off. It just a result of logic reduction. On the outside everything it is as
it should be.

"ALuPin" <ALuPin@web.de> schreef in bericht
news:b8a9a7b0.0405182314.45f47d4a@posting.google.com...

Dear Sir or Madam,

I have some phenomenon I do not know when synthesizing my VHDL
description for my
SRAM controller:

The .vho-file from Quartus is used for a timing simulation. When I
have a look at internal signals
of my controller like 'l_oe_bar', 'l_cs_bar','l_we_bar'
I see in timing simulation with Modelsim that they are right inverted
to my description, for example are
they resetted to '0' and not to my declared '1' in the VHDL
description.

The outputs of my controller are concurrently assigned like that:

OE_bar <= l_oe_bar;
CS_bar <= l_cs_bar;
WE_bar <= l_we_bar;

And yet they are inverted to the local signals.

I do not know why there seems to be a double inversion. What does
QuartusII do?

I would appreciate your help.

Kind regards