inv_delay

hai,
i am doing a simulation of inverter size 31.5/1 pmos and 25/1 nmos
driving 20 similar gates. it has

Average propagation delay = 413.45 ps.

AC power dissipation = 25.5ľw/MHz.

is there anyway other than increasing width of transistors to decrease
the delay and ac power dissipation.

and one more thing can i name my inverter that is driving 20 similar
gates as inv2x ? ( i am involved in std cell lib design for 1 micron
tech )

thanks a lot

regards
selvakumar

 

[S. Badel]

you can lower the supply voltage but i guess this is not something you can
do.

why are you using so large transistors?
a gate driving 20 similar gates will have approximately the same delay
wether it is 5/1 or 35/1.

<selvakumar_in@hotmail.com> wrote in message
news:63f7196c.0309232218.197f18a4@posting.google.com...

hai,
i am doing a simulation of inverter size 31.5/1 pmos and 25/1 nmos
driving 20 similar gates. it has

Average propagation delay = 413.45 ps.

AC power dissipation = 25.5ľw/MHz.

is there anyway other than increasing width of transistors to decrease
the delay and ac power dissipation.

and one more thing can i name my inverter that is driving 20 similar
gates as inv2x ? ( i am involved in std cell lib design for 1 micron
tech )

thanks a lot

regards
selvakumar