G
googler
Guest
Hello folks,
I am preparing for interviews for ASIC/logic design engineer position.
I came across a few questions for which I couldn't find a solution.
1. Using 3 registers and two two-bit full adders, how to count to 9
given that one clock cycle is only enough the delay of a full adder.
2. Given memory with 2n+1 values with n elements appearing twice in
different areas of the memory and 1 value appearing once. Design low
delay circuit that finds this 1 value.
If you know of other interesting/difficult interview questions, please
share.
Thanks.
I am preparing for interviews for ASIC/logic design engineer position.
I came across a few questions for which I couldn't find a solution.
1. Using 3 registers and two two-bit full adders, how to count to 9
given that one clock cycle is only enough the delay of a full adder.
2. Given memory with 2n+1 values with n elements appearing twice in
different areas of the memory and 1 value appearing once. Design low
delay circuit that finds this 1 value.
If you know of other interesting/difficult interview questions, please
share.
Thanks.