Interview questions:

Hi Fellow Verilog users:

I am preparing for an interview and have the following questions:

1. What should be the minimum clock for two flip-flops in series with
logic delay between them. Identical flipflop specs: 2ns setup, 3ns
holdtime, 4ns logic delay.

---------- ---------- ----------
| | | | | |
| dff |-----> | logic |-----> | dff |
| | | | | |
| | | | | |
---------- ---------- ----------

2. How are stacks designed using verilog

3. Where can find text/info online regarding similar academic questions
on logic circuit design.

Thank you for your time.

Salah
salah.kazi@gmail.com
salah.kazi @ gmail . com

 

Would you give me your salary?? I could only answer the first one...
atleast I deserve one thirds

Considering that both the flops are identical and they don't have any
propogation delay w.r.t clk, the max freq of operation is 1/(2+4) =
1/(6ns).

HTH,
Naren.

 

Boss,
He is talking minimum clock not maximum

 

[vic]

1. it should be 9 ns

clock pulse = tclkq + logic delay + tsu = 3 + 4 +2 =9 ns

2. stacks can be designed using fifo

3. search for hardware/vlsi interview questions, try specifically for
the company for your choice.

I hope that helps
-vinil