Internal clock

Hi,

My design is taking 16 clock cycles to generate the output for one data
.. So I
have wait to for 16 clock cycles to give another input.

Can any one suggest what I should do that my output comes when input
stream is given in each clock cycle.


I was trying to generate another internal clock based on my system
clock, such that in one clock cylce it generates another clock of 16
cycles.

How to generate internal clock?

Thanking you.

Sincerely,

Hiren Shah

 

[Rob]

What are you trying to do? Sounds like to me all you have to do is design a
16 clock cycle pipeline.


<hirenshah.05@gmail.com> wrote in message
news:1133640448.883976.230660@o13g2000cwo.googlegroups.com...

Hi,

My design is taking 16 clock cycles to generate the output for one data
. So I
have wait to for 16 clock cycles to give another input.

Can any one suggest what I should do that my output comes when input
stream is given in each clock cycle.


I was trying to generate another internal clock based on my system
clock, such that in one clock cylce it generates another clock of 16
cycles.

How to generate internal clock?

Thanking you.

Sincerely,

Hiren Shah

 

How do you figure out the delay is 16 clocks cycles? What's the
frequency you are using? If it is 0.13u 200M ASIC design, 16 clocks
cycles data path has tons of logic, maybe more than hundreds cells in
one path.

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.